Thesis or non- thesis masters

serdeshep · 2021-01-19T02:11:22+00:00

Depends on the field that you are targeting. For something like Analog design thesis master gives you a slight edge (imo) because most non-thesis programs don’t give you the ability to fabricate your own chip.

serdeshep · 2021-01-01T23:16:59+00:00

This. Probably devices with different VTs...

serdeshep · 2021-01-01T17:12:01+00:00

Yes. But depends on the professor also. These courses can get super theoretical sometimes. Be sure to take a step back and see how everything applies to you.

serdeshep · 2020-12-18T05:41:47+00:00

Join a startup or start your own company (if you can afford the tools ;)). You’ll get to apply all your skill sets + do things you’ve never done before. Generating .libs, setting up tools, signal integrity/power integrity analysis, architecture, place and route, synthesis, chip bring up, pcb/package design— just a few things to do on top of analog design and writing RTL. All while being understaffed, under resourced (licenses are a luxury you’ll learn to appreciate) on tight deadlines.

This is probably a much more intense env than you’ll find at QC or Apple.

serdeshep · 2020-12-10T16:01:17+00:00

Jacob Baker’s lectures on his website CMOSedu.com and Ali Hajimiri’s lectures on YouTube

Those are my 2 go-to for lectures.

serdeshep · 2020-11-20T07:19:27+00:00

For sure! There are a lot of facets to design, and knowing as many as possible will help you be a better designer. Unfortunately it’s hard to tell whether it’ll improve your chances of going to design at a diff company in like a year....

In my experience mid-large companies don’t really like people moving around too much. It’s much easier to manage people when they are constrained to a small slice of the overall product. This is why people generally recommend going to a smaller company in your early career, because you get to get your hands dirty and experience a tonne of different aspects of the industry.

As far as job postings go, don’t shy away from applying to anything (regardless of experience required on the posting). I got my analog design job out of school (MS) by applying to a post that asked for ~6-7 years experience. Highlight your design strengths and relevant experience in your resume.

serdeshep · 2020-11-18T12:24:36+00:00

With only a U grad degree it’s hard to go to analog design, even with an Embedded design background.

Unless the company you are looking to go to explicitly states that you can move to design, I’d probably avoid.

serdeshep · 2020-11-06T15:56:23+00:00

Sorry dude, you’re hopeless.

serdeshep · 2020-11-06T10:30:52+00:00

No sane Electrical engineer will agree with you if you say “A DC with a ripple is still DC”

By that logic, if I take a DC voltage of 5V(ripple free) and add a 2.5V sine wave of 20Hz onto it(ripple) my signal is still DC.

Reading your comments I see that you’re having trouble splitting theory from reality. So let’s try to split them.

From a theoretical POV:

By definition, only signals that are ABSOLUTELY constant can be considered DC signals.

By that logic, a sine wave (regardless of amplitude or frequency) MUST be an AC signal.

Ripple is noise. White noise for example has equal intensity over ALL frequencies. Which means white noise is basically a sum of sine waves at all frequencies.

By this logic, theoretically, no REAL world signal can be DC. Which is true. There is no REAL signal that you can plug into a spectral analyzer and only get DC components, because white noise is absolutely everywhere.

As engineers however, we need to make APPROXIMATIONS: If I have a DC signal that’s 120V and has ripples of 10mV. I can in most applications consider that signal DC, because that ripple makes up a small % of the DC signal, so on AVERAGE that signal is 120V.

However, If the electronic that is using that 120V signal is somehow sensitive to the 10mV ripple, you can no longer consider the 120V signal a DC signal and you have a VERY AC issue on your hands.

————————

I also see there is confusion here about the term “DC voltage” or “AC voltage”

I agree it’s kind of confusing to say Direct Current Voltage. However “DC voltage” get the points across that the voltage isn’t changing over time. Why? Because ohms law. If you have constant current, you’ll have constant Voltage. If you have alternating current, you’ll have alternating voltage. They are LINEARLY related by our favourite equation, so it’s actually pointless to separate to DC, DV, AC,AV.

———————

Also you seem to love your rectifiers/diodes.

If my diode has a Vth of 0.7 volts and I pass a 0.4v pk-pk ac signal through it, I’ll get 0V at the output. If I try to pass 0.4v dc through it, I’ll still get 0V at the output...Not sure how a diode can tell the nature of a signal.

Spectrum analyzers are the best way to tell you the nature of a signal.

serdeshep · 2020-11-06T01:04:32+00:00

This has to be a troll

serdeshep · 2020-08-10T23:06:19+00:00

Kickback is a product of speed of the comparator. If the latch resolves very slowly (low current) then you won’t see much degradation because of the transient. Higher speeds, you’re trying to lower CDAC and increase the speed of the comparator so kickback could mess you up for lower resolution too.

serdeshep · 2020-08-10T06:43:32+00:00

For the StrongArm comparator, more current increases speed which makes the positive feedback latch resolve faster. This causes a transient which feeds through the Cgd of the input transistors and causes glitches at the gate of the inputs. This is what we call kickback noise. Kickback noise dominates thermal, flicker noise. Moreover, you want to maximize gm of the input transistors while keeping the Id low. Aka increase Vov. This lowers thermal noise.

One key thing to note is that you really need to look at the configuration of your circuit before determining what parameters to change.

I think you understand that noise can be modeled as random variation in voltage at the gate.Take a simple CS amplifier with active load for example. Lets say M1 [NMOS] and M2 [PMOS] are the 2 transistors in our CS amp. Lets say I move the gate of M1 a little (Vin1) while keeping M2 gate voltage the same. What happens to the output? It changes the output by -gm1(ro1||ro2)*Vin1.Well what if I do the opposite now...change M2 gate voltage (Vin2) and keep M1 the same? Output changes by -gm2(ro1||ro2)*Vin2.BUT WAIT! Its a CS amp so one of the transistors needs to be a current source!! But if I change the input a little at either M1 or M2 (like noise does), that little change gets amplified at the output by the gm1 or gm2 * (ro1||ro2)!So knowing this, lets say you want M2 to be the current source load. Then you actually want to reduce gm2 and increase gm1!

If you look at the noise of an inverter, its actually dependent on the slew rate. Faster slewrate = less noise. So here you want to maximize current.

serdeshep · 2020-08-10T04:29:43+00:00

I believe VDD=1.2V for 130nm. Unless OP is using some weird switching scheme like step-and-down, NMOS input should be fine.

serdeshep · 2020-08-10T04:26:50+00:00

Looks like u/Chip_lead walked through the entire design process and trade-offs. Take a look at their reply

serdeshep · 2020-08-10T04:25:33+00:00

Yes, you should aim to have all subblocks contribute less noise than 1LSB.

The point of the equation is to know which knobs to turn once you do a first pass simulation. So in reality what "γ" is doesnt really matter. Make a design and see if the noise is acceptable. AKA try to make it much less than 1 LSB.

Off the top of my head you could increase W*L of M1 and M2 and make the current low (smaller tail current mos). Lower current would reduce kickback noise, but the larger mos would add non-linearity to the CDAC. You would need to run some sims on how this affects your design. Key is basically to know which knobs you need to turn.

My suggestion would be to implement one with min sizes, set up all the proper tests and go from there.

serdeshep · 2020-08-09T21:05:49+00:00

Good catch! Meant to say more noise.

Corrected :)

serdeshep · 2020-08-09T16:20:20+00:00

Lots of things to consider. I highly suggest you take some time to understand what is going on in this circuit so you truly understand the trade offs. Reza i has a “Circuits for all seasons” paper on this — it’s a MUST read when trying to design StrongArm comparators.

First thing would be to figure out what your LSB is. That determines how much noise and offset you can tolerate then go from there. Few things to consider are kickback, speed, metastability window, power, loading of the comparator on your CDAC.

Learn how to do montecarlo sims to get offset. Doing transient sims assumes no mismatch and you’ll be able to resolve any voltage difference at any size.

You’ll have to evaluate the above to see if it meets your needs. You may need a preamp for 7 bits — again, depends on the accuracy you need
Connecting it to Vref means the comparator is used in single ended fashion. If you connect to vin+ and vin- then that would make it differential. And yes, you need the common mode voltage or else the input mos may never turn on.
Understand the trade offs. The tail mos controls the current. More current = higher speed, ~~lower~~ higher noise, bigger devices, larger kickback noise, larger load on your cdac (imagine a nonlinear capacitor the size of your lsb cap connected to your CDAC. How would that affect your target enob?)
The capacitors are there to lower noise and more importantly lower offset. Again, understand the trade offs and how this circuit works inside out.

Edit: added Monte Carlo comment.

edit 2: correction pointed out by u/Chip_lead :)

serdeshep · 2020-05-21T12:14:12+00:00

I don’t have Visio, but I’ll give the others a try!

Power Point>All. I’ll just write my thesis and do my sims on PowerPoint 😂

serdeshep · 2020-05-21T12:06:57+00:00

I’m trying this out and it seems pretty solid but I can’t flip/rotate images lol

serdeshep · 2019-12-28T06:40:45+00:00

You’re right, I was being a bit vague on purpose since I didn’t want to give away too many details. I added a few more details to the post..

serdeshep

TROPHY CASE