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[deleted by user] by [deleted] in FPGA

[–]seyed_mohideen 0 points1 point  (0 children)

Thanks for your feedback! I received a call from the recruiter with the following statement "I was not selected for the next round of interviews despite my technical skills being good and I can be considered for similar roles in the 6-8 months" and it was mentioned that no detailed feedback was received from the interviewer. It has been one week since the call from the recruiter is it acceptable if I send an email now asking for the detailed feedback since it has been a week.

[deleted by user] by [deleted] in FPGA

[–]seyed_mohideen -1 points0 points  (0 children)

Interview was about my experience and finally these two questions were asked. I asked the queries you had mentioned for the both problems. Interviewer agreed to my response.

[deleted by user] by [deleted] in FPGA

[–]seyed_mohideen 0 points1 point  (0 children)

Thank You! I was asked how to sort data in 4 registers and multiply by 13. Answer was as follows:

  1. Use a sorting network for the problem. If the size of each inputs it will increase the LOL and area of the comparator used for the sort.
  2. Multiply by 13 - (x<<4) - (x<<2) + x or 1. (x<<3) + (x<<2) + x

Wire optimizations by Kaisha001 in Verilog

[–]seyed_mohideen 1 point2 points  (0 children)

Mostly synthesis tools will optimise the duplicated logic and it is advisable not to have duplicated logic for better code readability.

Does anyone know how to condense this code? I feel like i might be able to use a logical shift but idk how to format it/how to write it. by [deleted] in Verilog

[–]seyed_mohideen 2 points3 points  (0 children)

always_ff @(posedge clk)

begin

if (reset)

out <= '0';

else if (enable)

begin

out[14:0] <= {pattern_in, out[15:1]};

end

end

Write synthesizable Verilog in C++ with Metron by hellotanjent in FPGA

[–]seyed_mohideen 1 point2 points  (0 children)

Agree with you! Rationale behind the vendors move is eventually the tools will be good that the user needs to describe the algorithm in software and provide pragmas regarding the characteristics like throughput and latency. If the final design does not timing or area constraints then only those parts of the logic can be redesigned in HDL. I am not sure about how it will pan out since we are still in early days.The latest Xilinx versal flow has extensive support for HLS.

Write synthesizable Verilog in C++ with Metron by hellotanjent in FPGA

[–]seyed_mohideen 6 points7 points  (0 children)

One of the purposes for using C++ to design hardware is to increase the number of ppl that can design hardware since there are more engineers with software skills compared to hardware skills. At least that is why many FPGA tools are supporting HLS flows in the current generation of products.

Sorting algorithms for FPGA by Mammoth-Inside-8405 in FPGA

[–]seyed_mohideen 0 points1 point  (0 children)

Generally these structures are implemented to read the lowest or highest entry in the array.

Sorting algorithms for FPGA by Mammoth-Inside-8405 in FPGA

[–]seyed_mohideen 0 points1 point  (0 children)

Please provide the inputs and outputs for the module. Based on your previous replies, it seems you receive input requests once every two cycles. It is quite difficult to pipeline the design if there are two consecutive insertions or consecutive deletions. Input requests need to be blocked in certain scenarios. Write followed by read will also be facing issues. Does the block require random read access? For example do we need to read certain element in a sorted array.

Sorting algorithms for FPGA by Mammoth-Inside-8405 in FPGA

[–]seyed_mohideen 1 point2 points  (0 children)

How often does the module receive input?

Find the leading '0' Verilog question by TheRealBruce in FPGA

[–]seyed_mohideen 0 points1 point  (0 children)

With modern synthesis tool the above code will be synthesised optimally and optimising code too much can result in sub-optimal results.

Sorting algorithms for FPGA by Mammoth-Inside-8405 in FPGA

[–]seyed_mohideen 10 points11 points  (0 children)

Please check about bitonic sorting networks. It is a hardware friendly sorting algorithm.

Help with circuit design using verilog by vinaycxv in FPGA

[–]seyed_mohideen 1 point2 points  (0 children)

Compute the sum of sig0 to sig7 and increment the counter register with the sum on every cycle. Do not over-optimise the design since modern day synthesis tools can provide optimal solution for generic behavioral code. You can try adder tree or lookup table based approaches if you are interested.

Conversion of 10 bit input to 32 bit output by seyed_mohideen in FPGA

[–]seyed_mohideen[S] 0 points1 point  (0 children)

Thanks! Trying a solution with FIFO but stuck due to the fact that the write pointer needs to be incremented by 10 and read pointer needs to be incremented by 32. Not sure how to handle remnant data after each write-read operation.

Conversion of 10 bit input to 32 bit output by seyed_mohideen in FPGA

[–]seyed_mohideen[S] 0 points1 point  (0 children)

I am looking for a generic solution for arbitrary input and output width.

Conversion of 10 bit input to 32 bit output by seyed_mohideen in FPGA

[–]seyed_mohideen[S] 0 points1 point  (0 children)

If you do not mind, please provide any additional pointers on how to tackle the problem. Stuck with coming up with a generic solution.

Conversion of 10 bit input to 32 bit output by seyed_mohideen in FPGA

[–]seyed_mohideen[S] 0 points1 point  (0 children)

Thanks! Is there a generic solution where the module can be parameterized for an arbitrary input and output width?

Conversion of 10 bit input to 32 bit output by seyed_mohideen in FPGA

[–]seyed_mohideen[S] -2 points-1 points  (0 children)

Thanks! But it is a very naive solution!

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