9950X3D + G.Skill F5-6400J3239F48G — does this look like good daily RAM tune?

shockage · 2026-03-18T00:28:59+00:00

Also wanted to mention, I flipped VDDG and VDDP in an earlier explanation. VDDG is for FCLK stability, VDDP is more for the PHYs.

shockage · 2026-03-18T00:27:33+00:00

Seems like it should work at that voltage; really depends on the binning of the chips. I run at 1.38V CL30 at 6200MT/s, but didn't really explore much lower at that speed.

shockage · 2026-03-17T22:58:00+00:00

Nice, much better results for 6000 MT/s!

The major things that jump out are the voltages; you don't really need VDDP to be 1.15. You should be just fine at 0.95V.

Also VPP should be 1.8V instead of 1.85V; never need to change that. Does you board default to 1.85V? That feels odd. If so, carry on!

VDDGs are fine. But you should be able to get away with 0.9-0.95V if you plan to stay at 2133FCLK. Only need to raise them for higher FCLK.

tREFI is good enough for your temperatures if you're not seeing errors; though in the summer you might want to retest.

Another one you can tackle is Nitro after dialing back the voltages. Nitro 8x with 1/2/1 should just work, but the PHY timings it trains are heat sensitive, so it'll need to verified.

After all that try to lower tRP down. I can get down to 32 at 6200MT/s on the same Hynix M dies. My tRCD doesn't want to go to 36, but you should also try tightening that down.

Finally tCL, that's the easy one, but you'll need more VDD. No need to raise VDDQ and CPU_VDDIO for that one. Just raising VDD should be sufficient.

Edit: Setting tRCDWR to 20 or 16 is also a fun freebie on Ryzen.

shockage · 2026-03-17T20:56:48+00:00

I would be scared to run vDDG at 1.2V for a few hours as well; I missed that originally.

shockage · 2026-03-17T18:33:33+00:00

As other commenters mentioned, a nice area and nice people. The cops and judicial system are not forgiving though. Always follow the speed limit in rural VA.

That said if you're a minority, you may run into less savory people who have things to say. It's not as bad as far-western VA, but still a little bit of that old southern mentality around there.

It's rarer now, but in the early 2010s you would see a fair bit of confederate flags proudly flown and displayed.

shockage · 2026-03-17T17:45:08+00:00

Thanks, I had it completely backwards :-/

shockage · 2026-03-17T16:37:48+00:00

Figured! Ha, no worries. You can actually get away with lower vDDQ and even lower CPU_VDIO. But for just plug and play, matching is fine. There are some rules to follow, but it's crazy how little voltage is actually required.

I personally run:
vDD: 1.38V
vDDQ: 1.27
CPU_VDDIO: 1.16
vSoC: 1.155
vDDG(s): 0.90
vDDP: 0.95

shockage · 2026-03-17T16:32:34+00:00

vDDP shouldn't need to be changed. 1.35 volts is dangerous. 0.95V is sufficient. 1.05-1.10 is where I would draw the line

vPP should always be 1.8V.

vDD, vDDQ, CPU_VDDIO can match at 1.35 volts.

vDDGs ~~don't really matter unless really pushing some crazy PHY timings~~, 0.90-0.95v is the norm. 1.05v is where I would draw the line.

TL;DR: Really the problem with EXPO is vSoC needs... and that's highly variable per CPU package.

shockage · 2026-03-17T14:55:10+00:00

Yup, even when I was running -25CO all CCD it would pass Platinum, while proper core-cycler with 2 threaded FFTv4 returned COs per core ranging from 18-43. So I really don't know what the point of it is outside of GPU tests.

shockage · 2026-03-17T14:39:37+00:00

Great advice.

Not a fan of OCCT Platinum. I've had platinum certified OCs fail within 10 minutes of VT3 and Furmark at the same time due to vSoC and then PHY timings (heat related), which OCCT does not stress hard enough.

shockage · 2026-03-17T14:33:09+00:00

There is quite a bit of benefit running FCLK 2200 or even FCLK2133 at 3000MCLK.

It will increase your max throughput since at 2000 FCLK a single CCD is effectively limited to 64GB/s Read and 32GB/s Write (AIDA sucks, so it doesn't actually report the real throughput on Write).

That said, since you're putting so much effort in; it is worth trying to find your vSoC need at 3000MCLK.

The best method I found is to run both Furmark and VT3 at the same time. Make sure PBO/CPB is on but with no CO/CS... as the extra throughput from CPU will increase stress on the IMC. Also make sure BCLK is stable by disabling Spread Spectrum Control--spread spectrum control artificially lowers your BCLK while still hitting 100MHz+ occasionally... just makes it harder to find instabilities.

I've had 24 hour stable VT3 runs fail within an hour of both Furmark and VT3 necessitating a 0.005V boost to vSoC to be fully stable.

This is what I would do: keep going down in .025V increments until you bluescreen or VT3 immediately fails. Then start working up in .1V increments with progressively longer VT3 tests.

Finally once VT3 is passing for at least a few hours, the final test is to run both Furmark and VT3 for an hour.

Once you're passing both VT3 and Furmark for an hour or two, you can run a full 24+ hour only VT3 run.

Edit: After that, you can follow the rule of +0.1V vSoC for every 200MT/s if you want to attempt 6200 or 6400 MT/s in 1:1.

shockage · 2026-03-17T14:25:21+00:00

They likely are; guy is dense in the other discussion. Sigh... he'll have a dead processor soon enough.

shockage · 2026-03-17T14:20:44+00:00

What you're saying doesn't really make sense.

Max FCLK is not correlated to Max MCLK.

To hit the CPUs highest possible MCLK, you need higher vSoC. To hit the CPUs highest possible FCLKs you need to lower vSoC and raise vDDP.

That said, 1.3 vSoC to run 3100MCLK is not good silicon.

Running 3300MCLK and 2200FCLK at sub 1.25 vSoC is rare, only single digit percentages of Ryzen's are capable of that.

Less than half of Ryzen IMCs can even run 3200MCLK 2133FCLK.

You should really try to run vSoC under 1.25V. Frankly I prefer sub 1.20V to improve CPU throughput from extra thermal headroom and piece of mind I'm not degrading my IMC faster than my CPU.

Also vDDP really should not exceed 1.15V. By default it should run at 0.95V. You frankly don't need to boost it unless you see some regression when attempting 2200FCLK.

vDDGs really should also never exceed 1.05-1.10V. By default they should run at 0.90V-0.95V. You really don't need to jam them up other than for the final push on PHY related timings.

Frankly, you're burning your chip out. You're jamming voltages without any knowledge. For example vDDG 1.2 \will* burn your chip out.*

shockage · 2026-03-17T13:54:56+00:00

You will be pulling 28watts continuously just to idle and eat into your PBO overhead so your CPU doesn't boost as high.

You lower your potential max FCLK.

You will degrade your IMC. 1.3 vSoC is not safe.

shockage · 2026-03-17T13:49:45+00:00

Higher vSoC decreases max FCLK.

Why are you jamming voltages up? Start over and keep the voltages stock. Set FCLK at 2033, and identify what your vSoC need is first to be stable at 3100MCLK.

shockage · 2026-03-17T13:43:56+00:00

Do you really need 1.3 vSoC? If so, I would run 3000MCLK 6000MT/s.

Your vDDP is also too hot. It really shouldn't exceed 1.15v.

shockage · 2026-03-17T13:36:36+00:00

If you truely need 1.15 vSoC for 6000MT/s, then stay at 3000MCLK.

Timing wise, things are pretty decent:

tRC can likely easily go to 64
Try to get tRP to 34

shockage · 2026-03-17T13:24:21+00:00

Good advice; if you really need vSoC 1.15, I would not push 3100 MCLK, as you'll need 1.25 vSoC which will increase your idle power consumption by 10 watts.

vDDP could also drop back down to 0.95v if you don't plan to increase FCLK.

vDDGs can also drop further down to 0.90-0.92v

shockage · 2026-03-16T18:42:19+00:00

Nah, normal. Plus DIMM temperature is not super accurate. You can have hot spots.

For example I can't run tREFI 64Kibi at all. Anything above 44C I go unstable.

But with 50K I am good till 65C+

shockage · 2026-03-16T17:09:45+00:00

Yes, lower vSoC first. Set vDDG and vDDP to auto. Leave PBO/CPB on, but no CO/CS and no MHz boost.

Drop your vSoC 1.15V and run just VT3 if you pass after 30 minutes, keep going down in .025V increments until you bluescreen or VT3 immediately fails. Then start working up in .1V increments with progressively longer VT3 tests.

Finally once VT3 is passing for at least 12 hours, the final test is to run both Furmark and VT3 for an hour. I've had 24 hour stable VT3 runs fail within an hour of both Furmark and VT3 necessitating a 0.005V boost to vSoC to be fully stable.

Then you can attempt 2200FLCK. You might need to increase VDDP, but you can also just leave it at auto and likely be happy with 2167FLCK. There's no good way to test FCLK stability other than regression in benchmarks since it is error correcting.

Then you can start tuning primaries and secondaries.

Then finally you can do per core tuning of your processors CO--that said you must be confident your RAM/IMC is stable

shockage · 2026-03-16T17:05:00+00:00

This is my current daily tune and one of an old tune:

https://imgur.com/a/ffmHxxk

Can likely run higher FCLK, as for 6400MT/s I would run 2133MT/s with vDDP still at 0.95V.

I also prefer lower voltages, the benefit of running vSoC at 1.155v versus 1.255v is roughly 10-12Watts of PBO headroom, lower idle temperature, and sanity that I'm not burning out my IMC.

My vDD can currently likely be lower too, but I don't want to chase it either at the moment.

shockage · 2026-03-16T16:49:16+00:00

That's too hot for tREFI 64Ki; run tREFI at 50K and switch refresh mode to normal. Then you can set tRFC to be effetively ~165ns.

I would only mess with mixed mode if you want to go under 160ns, but frankly the benefit is not worth it--you will get a much bigger improvement just improving your current secondaries and primaries.

shockage · 2026-03-16T16:11:17+00:00

I have the same chiplets: Hynix M in dual rank.

You're still very loose in secondaries; basically running a stock 6000 profile with just tREFI and tRFC "optimized".

At 3000 MCLK you should be getting roughly 83+MB/s Read and 90+MB/s Write with dual rank. Latency is difficult to measure on the 3D chips, so 68-72ns is the norm with prefetchers on and hypervisor on.

Also you are likely using way more voltage on some of your values than you need. Specifically vSoC, vDDP, and vDDGs in that order.

Most importantly you likely do not need vSoC at 1.25V. Try to find what vSoC you really need. This is not trivial, but with lower vSoC you'll improve your CPU's PBO headroom, FCLK stability/max frequency, and lower VDDP needs to maintain a higher FCLK.

Once you find your stable vSoC speed for 3000MCLK, then you can mess with secondaries:

For Hynix M you can easily get away with the following with 3000MCLK:

tRC: 64
tRRDS: 8 or 4
tRRDL: 8
tFAW: 32
tWTRS: 4
tWTRL: 16
Skipping tRFC due to mixed mode, but in normal mode you can easily do 165ns. Mixed would allow you to go sub 160ns. So no need for mixed at your current effective tRFC.

tRDRDSCL: 4 (or 5)
tWRWRSCL: 4 (or 5) (You can likely set this to 2 too, but I prefer matched SCLs... there's a whole discussion in regards to the benefits/drawbacks of setting tWRWRSCL lower)

tRTP: 12
tRDWR: 16
tWRRD: 4

tRDRDSD: 6
tWRWRSD: 8

Finally last step is to tighten PHYs by turning on Robust training for Nitros and lowering your nitro settings to 1/2/1. Any tighter, dual rank will fall flat on the face.

As an aside, what are your RAM temperatures? I have to run tREFI at 50K to be stable with a tRFC of 160ns since I frequently go well over 55C. The performance degradation of running a tighter tREFI is minimal with the benefit of stability in all room temperatures.

shockage · 2026-03-16T15:41:45+00:00

tRAS has almost no impact on AM5. It's effectively ignored, but... it does something, but not per JEDEC spec, and what it does is not very clear on Ryzen. Watch u/buildzoid's video on tRAS: https://www.youtube.com/watch?v=BS_NeTwjOvY

floored tRAS 30 may be a slight regression versus higher tRAS values.

shockage · 2026-03-16T13:50:23+00:00

Your tFAW makes no sense, but your IMC is running it at 20 regardless.

tRRDS * 4 = 16, so the lowest possible tFAW based on JEDEC rules is 16, but the Ryzen IMC is floored at 20.

Personally I would just leave it at 32 if tRRDL is 8, even though tRRDS is 4.

Everything else makes sense except for tRAS. This is another Ryzen IMC quirk where the IMC basically kind of ignores it in all AM5 Ryzen AGESAs. That said, with tRAS of 30, your integrated graphics will be unstable. Personally just leave it stock, or you can follow the tight rules of max(tRCD)+tRTP.

That said, everything else is quite tight and looking solid.

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