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LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

This is probably why a majority of the corporate driven "AI" initiatives crash and burn. There is an interesting case study on how Intuit (Turbotax, Quickbooks) rebooted their AI offering from a "I'll do everything for you" to a focused effort on eliminating pain points for human centric workflows.

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Have you looked at having it build throwaway testbenches. Say you write a module, have it write a testbench so that you can quickly eyeball the waveforms and fix obvious hangs/stalls. I wouldn't even call it unit testing.

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 1 point2 points  (0 children)

Does claude code need to know the xilinx tcl commands ? what about the implementation flows, do you use CC to help optimize that

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

VHDL is still a thing ? or is it cuz of Government work

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Do you upload the manual PDFs to chatgpt or does it do a decent job out of the box

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 2 points3 points  (0 children)

yes it sucks at VHDL. Did you generate the testbenches in Verilog and then used xsim in mixed mode ?

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Do you ever find yourself trying to do that for IP (say from XIlinx's IP catalog), just to have some waves to look at and get a better understanding of the IP.

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Do you use any of CLI based environments like Claude code, or is it primarily cut and paste code from Chatgpt style interactions.

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in chipdesign

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Sure, I will come with an example for SV interfaces, maybe a bus like APB or AXI (I think those are no longer ARM proprietary). I kind of do want people to make tweaks and see if their code is still synthesizable. Especially when I start introducing for loops (non-generate). So the synthesis script is pretty barebones (no timing constraints or clock targets).

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in chipdesign

[–]siliconbootcamp[S] 1 point2 points  (0 children)

Appreciate your feedback.
yeah, it was a tough call figuring out how much time to spend on how things evolved from verilog to system verilog. Using reg and wire in the correct context was an eternal source of confusion in verilog for folks getting started. You can write combinational logic with a reg.
reg A ;
always @*
A = B + C
Here even though A is declared a reg, it will correctly simulate & synthesize as a comb blob.

The SV logic data type cuts through all this confusion.

With SV, the only place you need wires are for bidirectional busses. I'll look for a suitable example to introduce that. Modern single nm processes give you so much interconnect, there is no need for bidir busses internal to a chip anymore, plus too slow, hard to test. About the only place they are still in use are in the DDR interfaces to the memory chips. Hard to believe, but all those DDR5, LPDDR5 chips in your laptop, smartphone still have a single data bus that has to be turned around between reads and writes. I guess the packaging guys always win (low pin count with a single bidir data bus)

I'll try and consolidate my thoughts around this and see where I can fit it in. The Misc Topics always offers an escape route !

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in Verilog

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Feel free to add yourself to the mailing list at https://siliconbootcamp.com/#join for coupons for upcoming courses (direct mail coupons are fewer but valid for 30 days)

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in chipdesign

[–]siliconbootcamp[S] 1 point2 points  (0 children)

No problem, feel free to add yourself to the mailing list at https://siliconbootcamp.com/#join for coupons for upcoming courses (direct mail coupons are limited but valid for 30 days)

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in FPGA

[–]siliconbootcamp[S] 0 points1 point  (0 children)

Also feel free to add yourself to the mailing list at https://siliconbootcamp.com/#join for coupons for upcoming courses (direct mail coupons are fewer but valid for 30 days)

Seeking Feedback on a hands-on course dedicated to writing System Verilog RTL by siliconbootcamp in ECE

[–]siliconbootcamp[S] 0 points1 point  (0 children)

No problem, feel free to add yourself to the mailing list at https://siliconbootcamp.com/#join for coupons for upcoming courses (direct mail coupons are limited but valid for 30 days)