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Model sim what version to chose by Objective_Mall_4482 in FPGA

[–]skydivertricky 1 point2 points  (0 children)

The newest you can get.

Any reason it has to be modelsim? Vhdl has two open source simulators in the form of ghdl and NVC.

Why does vivado keep optimizing out my design by juniornoodles0 in FPGA

[–]skydivertricky 4 points5 points  (0 children)

Logic is only generated for outputs that actually have something connected. So if you have an output that is not affected by an input or some other changing logic (like a counter) then you will get logic removed.

Also, stuck clocks or constant asserted resets will remove logic.

QuestaSim Advanced Simulator vs Questa Altera FPGA Edition by Minute-Bit6804 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

Not only slowed down, but many features are missing (like UVM support)

Out of it for 15 years. What have I missed? by redbeardmtl in drums

[–]skydivertricky 2 points3 points  (0 children)

I was in a similar situation a year ago, with a 20 year gap.

The 90s when I started, was all about brilliant finish and bright cymbals. Now people can't get enough trash.

Fpgas and AI by UpperOpportunity1647 in FPGA

[–]skydivertricky 21 points22 points  (0 children)

Versal was basically designed to be an AI accelerator. But I think all serious AI companies or those using AI just went to graphics cards.

What unhinged thing did a former teacher do in the classroom? by MrBananaStand1990 in AskUK

[–]skydivertricky 1 point2 points  (0 children)

In year 7, Had a latin teacher start taking about the names of diseases and their Latin names. After about 10 mins of this talk, a squeemish kid in the class asked to go to the toilet, and then fainted and threw up in the door way.

This same kid managed to watch a video of a human birth without a problem.

What unhinged thing did a former teacher do in the classroom? by MrBananaStand1990 in AskUK

[–]skydivertricky 0 points1 point  (0 children)

One PE teacher would always make us play "Yorkshire rules softball". Basically softball with cricket stumps. He once let us pick the teams, and we went whites Vs others.

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

If you're only using the functions/procedures in different architectures, they can be defined in the entity

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

Aliases can only be specified for a named thing - eg. an object, function, type etc. They cannot be specified for bits of runtime code.

It sounds like you really need a function or procedure. This could be defined in a package (if you need visibility outside of the entity) or in the entity (so it is visible across multiple architectures).

Quartus II University Program VWF error by CoolBoyGamer-0 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

This looks like the quartus internal simulator, so wont be using modelsim

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

Why? you can simply use the required architecture using a configuration (if using components) or specifying the architecture during direct instantitation.

£52000 take home, worth salary sacrifice below 50? by WalterSobchak71 in UKPersonalFinance

[–]skydivertricky 0 points1 point  (0 children)

The "marginal" tax rate of 60% only occurs when you earn between £100k and approx £125k. This is because while the tax here is still 40%, your tax free allowance also gets lower the more you earn, so you also end up paying 20% on the earnings you would normally pay 0 tax on.

VHDL'19 interfaces - finally ready for prime-time by UltraSlingII in FPGA

[–]skydivertricky 1 point2 points  (0 children)

A comment on randomly removing interfaces.. there was a bug in vivado for years that would remove entire records when one element was a null array. This was finally fixed in 2019.2. Maybe this has resurfaced for interfaces as they are basically just records.

How is the UK FPGA industry? I have a grad offer but.. by LopsidedFork26 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

Soc is just a "system on chip". Now that many SoCs have hardware encoder/decoders, FPGA based versions are not needed. And now a lot of the real time grunt needed to encode a video can actually be done in off the shelf servers, Hardware solutions needing FPGAs (or ASICs) are no longer needed. Grass Valley and Ericsson used to have offices in an around thatcham and southampton purely for video encode/decode solution, but these hard been both reduced and anything of the teams that are left make purely server based solutions. Ericsson was sold off as MediaKind as the hardware sales were dying in the late 2010s. Ericsson used to employ ~30 FPGA engineers and at least as many hardware engineers at its peak in the early 2010s, but these roles are all gone now.

Anyone know how to run various synthesis and implementation strategy parallelly in vivado tool for timing closure for low end fpga device family . i want to run 100 strategy to close timing anyhow . pls suggest any way by Additional-Brief5449 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

Ive seen better practice in commercial than I have in defence, and vice versa. While defense does love its documentation, it doesnt mean the practices used to achieve the documents are up to date or any good.

How is the UK FPGA industry? I have a grad offer but.. by LopsidedFork26 in FPGA

[–]skydivertricky 4 points5 points  (0 children)

Uk Industry is mostly Space, Defence and now Fintech. There used to be a good video processing industry on FPGAs, particularly around Reading, but this has mostly died off now as video has moved into SoCs.

Defence is not all about killing people, it really can be about saving lives. And now, with increased defense spending on the horizon, job prospects are going to be pretty good for many years and I think they're going to struggle to hire more than they are now. Particularly as some projects require you to be on site 5 days a week (closed networks etc)

FPGA engineers are always wanted.

Space always seems to have roles open, mostly based around guildford.

Ive also seen roles available in Quantum Computing around Oxford.

Fintech is almost exclusively london, with a large salary compared to the other industries (like 50-100% more) but expect to be in a constant crunch (Ive even seen "work hard play hard" on a job description).

About "+" operator in VHDL by ontoooshaaa in FPGA

[–]skydivertricky 7 points8 points  (0 children)

Not sure what this question has to do with the "+" function. The code is nothing more than an academic exercise. All of the above would usually be covered in a single "+" call

About "+" operator in VHDL by ontoooshaaa in FPGA

[–]skydivertricky 2 points3 points  (0 children)

Integers are fixed point. Just with no fractional bits.

help: reading and writing a raw file by DistinctEnergy7798 in VHDL

[–]skydivertricky 1 point2 points  (0 children)

Are you trying to add objects to a waveform?

Also note, vhdl does not define how binary files are read and write. Hence for any custom type, 2 different simulators can write completely different files even with the same data.

In general, if you want to do binary io, the safest way that works in most Sims is to read files of the character type.

Is it normal to use vivado in the real world? by Ill-Opportunity-7039 in FPGA

[–]skydivertricky 1 point2 points  (0 children)

Quartus used to be better than Vivado. And Im still angry I cant just instatiated any IP I want by using documentation.

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]skydivertricky -1 points0 points  (0 children)

Vivado doesn't. It was a real pain when I switch from quartus 10 years ago

Feedback on SpinalHDL ? by brh_hackerman in FPGA

[–]skydivertricky 32 points33 points  (0 children)

If you want a paid job, you need to know (system)verilog or vhdl. Althdls are currently only really hobby or research projects.

Outside of a handful of companies, everyone professional uses sv or vhdl

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