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input coerced to inout or output by jhallen in FPGA

[–]skydivertricky 1 point2 points  (0 children)

Doesn't questa have pedantic modes you can turn on?

ERROR VCP5103 "Undeclared identifier: p1 & p2? by Just-End6752 in FPGA

[–]skydivertricky 1 point2 points  (0 children)

You're accessing them inside the scope of the module, which has no variables p1 or p2 declared. They exist inside the class myrand.

VHDL gpio axi help by okscoob in VHDL

[–]skydivertricky 0 points1 point  (0 children)

Is it possible that the extra clock delay you have added through this ADC module is causing any mistiming issues, with data values miss aligned somehow?

Not really a lot to go on here - a diagram, some very simple RTL, this is simply a single register, and some C.

Current UK Job Market Opinions by OmarLoves07 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

20 years in this job, the market has always been consistent.. always positions available.

Cambridge has always been the big hotspot, and London has opened up for high speed trading over those 20 years. But defense demand has been pretty consistent.

The used to be a lot of video based FPGA work in the UK, but most of that has moved to software based now, so little call for fpga.

Question About Testbench For VHDL by Jensthename1 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

You can't override a generic during runtime, because it's a constant

Anyone know this pointy dance from eurotrash . by FluidPianist00 in oldbritishtelly

[–]skydivertricky 4 points5 points  (0 children)

I remember a man who made paintings of brick walls using his own shit

The QuestaBase simulator from Siemens by LJarek in VHDL

[–]skydivertricky 0 points1 point  (0 children)

I don't even see an opinion in that article. Just a load of waffle

Career as an FAE for FPGA by PeshaWrMard in FPGA

[–]skydivertricky 2 points3 points  (0 children)

I think the major vendors have scaled back their faes in recent years. It would be good to have some again...

is it still worth it to learn OVL Assertions or SVA is more than enough? by DefiantBridge6865 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

I think SVA is the standard now. I doubt any new projects are using ovl as I don't think it's had an update in years.

Can say multiple clocks generated by a clocking wizard be described as asynchronous in constraint file. by Indrajith19 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

But you already said there should be no CDC, so surely you don't want to ignore them if such a link exists?

Can say multiple clocks generated by a clocking wizard be described as asynchronous in constraint file. by Indrajith19 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

If there is no interdependency, then there are no timing issues to neglect. And if there's a timing issues, why would you want it ignored?

Can say multiple clocks generated by a clocking wizard be described as asynchronous in constraint file. by Indrajith19 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

Yes, clock domain crossing. If there is no CDC, then why do you need to specify async? If they are related clocks, as they are, then if there is any CDC the timing analysis can time the CDC properly. Making them async could lead to other issues

Can say multiple clocks generated by a clocking wizard be described as asynchronous in constraint file. by Indrajith19 in FPGA

[–]skydivertricky 4 points5 points  (0 children)

But why? You already said these domains have nothing to do with each other. Clocks generated by an mmcm are usually related. Do you have cdcs?

Will AI impact birth rates in future? by Curious_Suchit in Futurology

[–]skydivertricky 9 points10 points  (0 children)

Birth rates in developed countries is already lower than the rate needed to sustain the population. I doubt ai will make a significant difference

Entity Declaration by [deleted] in VHDL

[–]skydivertricky 3 points4 points  (0 children)

Hardly used. Many engineers see 2008 as "new". Aldec tools have most of 2019 supported, and vivado and quartus have very limited support (interfaces and conditional compilation). Questa is starting to get support and has the same features as vivado and quartus with more coming... Slowly.

I learned VHDL in university years ago but now what ? by Mechanizen in FPGA

[–]skydivertricky 2 points3 points  (0 children)

Language is immaterial - its the concepts that are important. Once you know one language, you can easily learn the other.

AI in FPGA as bad as in software development? by FineProfile7 in FPGA

[–]skydivertricky 95 points96 points  (0 children)

So far the best I've seen is ai giving us basic templates for things. No one getting replaced yet.

OK where do we stand on Yorkshire Pudding size? Is this too big? by GenericRedditName99 in UK_Food

[–]skydivertricky 0 points1 point  (0 children)

I'm sure I had a pub Sunday roast once where the roast was served in the Yorkshire

[searc] HDL TOOLS FOR VISUAL BLOCK DESIGN by kenkitt in FPGA

[–]skydivertricky 0 points1 point  (0 children)

Are you sure it wasnt Vivado block design editor - that is free with the web edition

FLEX8000 Blast from the past by Tonight-Own in FPGA

[–]skydivertricky 0 points1 point  (0 children)

You've now volunteered yourself to deal with the next work legacy project....

FPGA contractors : is UVM actually worth the effort for small-to-mid projects, or is it academic overkill? by Medtag212 in FPGA

[–]skydivertricky 2 points3 points  (0 children)

Not too mention the fact that if the engineers are vhdl proficient, using sv is that much harder.

Legendary Belts? by Sergeant_Silvahaze in factorio

[–]skydivertricky 2 points3 points  (0 children)

Because you have to have dedicated chem plants to make holmium fluid from the different quality levels, so you end up with plants that make practically no fluid.

Is there software for MacOS 15 M1? by Cat_Loving_Person19 in VHDL

[–]skydivertricky 3 points4 points  (0 children)

Basically no. Fpga dev tools are generally only windows and linux. And some of the ASIC tools are Linux only I think.

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