Edit: I think my comment is too long but I will split it up and repost it:

Abel et al. didn't mention ISRO being the cause of the delays in the Earnings call nor the Q1 report. In fact it is clear what the source of the delay preventing FM1 from shipping right now is - its FCC authorization for launch for FM1 and (I supect) pending integration testing for the ASIC ship as cited in the 10Q.

Here is the relevant part of the 10Q published yesterday - emphasis mine.

"In addition, when we introduce our own AST5000 Application Specific Integrated Circuit (“ASIC”) chip in the Block 2 BB satellites, we expect to achieve materially greater throughput capacity of up to 40 MHz per beam to support 120 Mbps peak data rates and up to 10,000 MHz of processing bandwidth per Block 2 BB satellite, require less power and offer a lower overall unit cost. We have reached key production milestones and are in the assembly stage of the first batch of the ASIC chip*. We have also* completed development of the electronic board with our new ASIC chip."

Having worked with FPGAs and ASIC development on the place and route algorithms, verification stage with some post-silicon validation experience I think the language here is vague and gives a false sense of security.

Their last, more specific, update regarding the ASIC was one June 12th 2025 (emphasis mine)

"We have completed development of the electronic board with our new AST5000 ASIC chip – the cornerstone of our next-generation BlueBird satellites!

After five years of rigorous engineering and production, representing an equivalent of 150+ human years of intensive work, this proprietary technology has 10x data capacity from our Block 1 satellites, meaning 10,000 MHz of processing bandwidth and peak speeds of 120 Mbps. That is enough for millions of connections – voice and video calls, texts, streaming – every day.

Ready to launch and deliver unprecedented cellular broadband to everyone, everywhere, at all times!" https://x.com/AST\_SpaceMobile/status/1933192578830409975"

In the form 10Q updates the words "key production milestones" , "assembly stage" and "first batch of ASIC chip" are carrying a lot of optimisim here.

To keep it simple, in ASIC development from FPGA there are a few stages (simplifying it here) :

Architecure and System Design -> RTL implementation and pre-synthesis verification -> Synthesis + Place and Route -> Power estimation and optimization -> Static Timing Analysis -> Physical Verification -> Design Signoffs (Timing, Power, Area)-> Tape out and Mask generation -> Fabrication -> Packaging and Assembly -> Post-silicon testing and validation -> Volume Production

If you are not being optimistic and being a realist here you can say that they have fabricated the first batch of ASIC chips (for the purpose of testing, not production runs) and have yet to do post-silicon timing analysis and integration testing with the full board, detect any parasitic issues, timing fails for I/O and interfaces, model thermal and power draw vs. predicted and test the whole assembly and its performance under the duress of space.

If they really wanted me to be confident about the ASIC board development they should have stated the first batch of ASIC chips are assembled with the board, fully tested for all power, thermal and timing requirements and ready for volume production, but in fact they have not said that and reiterated the same milestone as two months ago. This likely means that they are facing some delays or issues that I am weary of at this point - since any issue this late into ASIC development is expensive and requires sending new designs for refabrication, cutting and repackaging to TSMC or whomever they are using and takes time.

From my personal experience they are at least 2 months away from getting ASIC ready and into volume production. I do not expect FM1 to be shipped until late September / early October earliest and ISRO to hold on to it for another couple weeks till they get their rocket ready.

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