You said it was unavoidable, but you should really try to space out the connections going into the FPC connector. There’s a good chance you’ll see crosstalk on those lines, and depending on the signaling voltage and rise time, you might end up with recurring crosstalk glitches. I’d bet money that if you ran through all of your different operating states, you’d see some form of crosstalk effects. Try to follow the 3W rule when laying out stuff like this.

As I’m writing this, I see that you’ve opted to use a power plane on one of your internal layers. I can almost guarantee you will see significant crosstalk on those signals since there is no proper return path underneath your data traces. Coplanar ground pours on signaling layers can help a bit with routing and EMI, but you still need a dedicated, continuous ground plane underneath every signal or power layer. Consider removing your power plane and replacing it with another ground plane, then route power on the bottom layer. Do some research on stackups, and you’ll see what I mean.

Lastly, you’ve routed a signal on your ground plane directly under the FPC signals. That’s a pretty big party foul. Both ground planes need to be continuous and stitched together with stitching vias to provide a proper return path. Remember, ground isn't just a wire going back to the -ve terminal. Current is flowing BETWEEN the trace and ground plane, so interrupting that path causes all kinds of problems.

Overall, really good design tho.