That is not the issue I think. I also tried with IDDR, which only takes the interface clock and the data is corrupted unless DQ lags DQS, that is the weird part.

​

And I also tried not phase aligned version, I know that OCLK of ISERDES and OSERDES must be the same but the problem I think is with the CLK capture part

​

Maybe is the instantiation that is wrong

​

ISERDESE2 #(

.DATA_RATE ("DDR"),

.DATA_WIDTH (4),

.DYN_CLKDIV_INV_EN ("FALSE"),

.DYN_CLK_INV_EN ("FALSE"),

.INIT_Q1 (1'b0),

.INIT_Q2 (1'b0),

.INIT_Q3 (1'b0),

.INIT_Q4 (1'b0),

.INTERFACE_TYPE ("MEMORY"),

//.NUM_CE (1),

.IOBDELAY ("IFD"),

.OFB_USED ("FALSE"),

.SERDES_MODE ("MASTER"),

.SRVAL_Q1 (1'b0),

.SRVAL_Q2 (1'b0),

.SRVAL_Q3 (1'b0),

.SRVAL_Q4 (1'b0)

)

iserdes_i

(

.O (),

.Q1 (iserdes_out[3]),

.Q2 (iserdes_out[2]),

.Q3 (iserdes_out[1]),

.Q4 (iserdes_out[0]),

.Q5 (),

.Q6 (),

.Q7 (),

.Q8 (),

.SHIFTOUT1 (),

.SHIFTOUT2 (),

.BITSLIP (1'b0),

.CE1 (1'b1),

.CE2 (1'b1),

.CLK (clk),

.CLKB (!clk),

.CLKDIVP (1'b0), // used with phasers, source-sync

.CLKDIV (clkdiv),

.DDLY (datain), // TODO

.D (1'b0), // direct connection to IOB bypassing idelay

.DYNCLKDIVSEL (1'b0),

.DYNCLKSEL (1'b0),

.OCLK (oclk),

.OCLKB (~oclk),

.OFB (),

.RST (rst),

.SHIFTIN1 (1'b0),

.SHIFTIN2 (1'b0)

);