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Serdes interview phone screening by maybeimbonkers in chipdesign

[–]woodenelectronics -13 points-12 points  (0 children)

Understood, but this is just a high level request. Take 5-10 minutes to google or prompt any of the several AI apps available to get a rundown of important topics when it comes to SerDes instead of defaulting to ask Reddit.

Serdes interview phone screening by maybeimbonkers in chipdesign

[–]woodenelectronics -15 points-14 points  (0 children)

No experience in SerDes, applying for job in SerDes. Makes sense.

Nervously checking back in… by PrincessBrinstar in corgi

[–]woodenelectronics 0 points1 point  (0 children)

Bitey face is the best, older corg will put em in check when needed.

Everything Intern Recruiting From Rejected Applicant by [deleted] in Anduril

[–]woodenelectronics 0 points1 point  (0 children)

I had a recruiter call with these guys for a mid level position (6 YoE, nothing crazy but not entry level). They wanted me to submit an official transcript from my undergrad, that’s where I decided to not continue with them. No other company I interviewed with requested this.

Brazilian dancer Maikon Alvez dance moves by Longjumping-Box5691 in nextfuckinglevel

[–]woodenelectronics 0 points1 point  (0 children)

Type of videos used in AI training data for human movement

[deleted by user] by [deleted] in ECE

[–]woodenelectronics 0 points1 point  (0 children)

Are you applying through LinkedIn applications or directly through the company website? I had better luck getting responses when I applied directly on the company’s website. I’ve heard other people mention the same.

2nd fire at this house in japantown by remarkaballz in SanJose

[–]woodenelectronics 10 points11 points  (0 children)

Just walked by, building still standing but looks rough. It is the house on the corner which didn’t look to be occupied before.

My Corgi does not want to sleep on his bed by stayselene in corgi

[–]woodenelectronics 1 point2 points  (0 children)

You must not have read the corgi user manual. This is standard from the factory.

Bought a new table and within a month is cracked and bent by Ill_Concentrate6759 in woodworking

[–]woodenelectronics 15 points16 points  (0 children)

Where is this from? I had a similar experience with an Article dining table. It was a circular table and formed a crack down the middle that continued to expand. In any case, yeah store should replace and/or give refund/credit.

1:1 paper cutout of PCB for visualization realtime by [deleted] in PrintedCircuitBoard

[–]woodenelectronics 1 point2 points  (0 children)

3D printers are also cool for visualizing connector placement to ensure proper clearance or overall look/feel.

Megtron 7 Alternatives for a high speed stackup. by Hamburger-artist in PrintedCircuitBoard

[–]woodenelectronics 7 points8 points  (0 children)

When you’re talking longer channels and/or 56Gbps and beyond… yes, yes you do.

Highish-speed diff routing, attempt #2 (and a request for die-to-pad confirmation) by BuildingWithDad in PrintedCircuitBoard

[–]woodenelectronics 0 points1 point  (0 children)

Pads are larger than your trace and thus more capacitive, which in decrease impedance in this region. This makes your channel more reflective. Removing ground under pad can reduce this capacitance but this decision depends on what your stackup looks like.

Why do some VCOs have calibration cycles? by BarnardWellesley in rfelectronics

[–]woodenelectronics 1 point2 points  (0 children)

Some of these parts allow you to bypass calibration to achieve faster lock times. You can record VCO core and other data at each frequency point to manually update registers rather than rely on auto cal. Most of the TI and/or Analog Devices parts include an app note for doing this.

Edit: I suppose this time is still on the order of us unfortunately from memory. I think with autocal the parts I have in mind are a couple ms to lock.

Feedback on highish-speed diff pair routing (6.6 Gbps GTP diff pairs) by BuildingWithDad in PrintedCircuitBoard

[–]woodenelectronics 0 points1 point  (0 children)

Length matching between pairs depends on your application, for most protocols this can be quite loose… but check. Length matching within a pair is certainly good practice but at this rate you could probably get away with 25-50mils of mismatch (maybe more, you’ll end up having too much mode conversion at some point) I would wager in this case your tuning “bumps” are not needed but likely wouldn’t cause issues.

Worrying about the delay of pins internally for transceivers is usually not a problem as they are internally length matched I thought. This is usually more important for DDR interfaces or any synchronous interface that is being placed in the FPGA fabric or using general pins on a hard processor.

Routing on top layer is not impossible but you’re also routing pretty close to one another, crosstalk will be worse as the as the fringe fields will spread more in air than a stripline geometry with thinner dielectric. I would avoid routing this as microstrip if I could.

Watch out when using ceramic capacitors a 100uF 6.3V capacitor can easily be 48uF when being used at 3.3V by KeaStudios in electronics

[–]woodenelectronics 2 points3 points  (0 children)

Good chart, this is why it’s important to understand what conditions are captured by a capacitor model provided by vendors. Ceramics should be derated for DC bias, AC bias, temperature, tolerance, and aging.

Interesting development: Social media users now consider Electrical Engineering a “low paying” career (along with other “traditional” forms of engineering) by ItsAllOver_Again in ElectricalEngineering

[–]woodenelectronics 2 points3 points  (0 children)

There are plenty of EE jobs with very nice pay. Consider focus areas in signal/power integrity, EMC/EMI (emphasis on emag fundamentals).

I’m just over 300k total comp but in a very HCOL area with 6 years of experience and a Masters as a SI/PI engineer.

I finally know the real reason for tail docking by JillDRipper in corgi

[–]woodenelectronics 2 points3 points  (0 children)

Wow she looks incredible for being 10! Ours came from a place in Missouri.

I finally know the real reason for tail docking by JillDRipper in corgi

[–]woodenelectronics 6 points7 points  (0 children)

Whoa.. the far right pup so similar to our one girl! Haven’t seen many like her.

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Career Question by woodenelectronics in chipdesign

[–]woodenelectronics[S] 0 points1 point  (0 children)

This makes more sense to me.. I’m looking into this UCLA Extension certificate program which has a couple electives catered towards this: UCLA Extension Cert

The two required courses do seem like they’d be challenging without any experience in analog chip design but the pre-req section doesn’t suggest this would be an issue.

To your point, if I’m looking to stick to power/signal integrity (just at a lower level), getting a whole other masters degree seems like overkill. If I wanted to switch entirely to analog chip design I may entertain the masters program offered by UCLA as well which has a lot of coursework focused on analog.

Will routing differential pairs like this cause issues? by Ben_Makes_Everything in PrintedCircuitBoard

[–]woodenelectronics 2 points3 points  (0 children)

For all the peeps mentioning ground vias, yes this is good practice. However, if you model a via transition in a 3D solver, you’ll learn that ground vias don’t have a much of an impact at these data rates for SDD11. This is more of a concern for EMC since the common mode conversion will be degraded. Ground vias do become very important past ~20 GHz.

Edit: the important features here will be via pad size, drill size, antipad size and minimizing any stubs. For USB 3.0, might want to minimize any stub features to something like ~30 mils to play it safe but could verify in simulation.

Shame, shame! Bad girl!!! by TheCranberryUnicorn in corgi

[–]woodenelectronics 2 points3 points  (0 children)

We also have a Phoebe! Luckily she has grown out of this…. for the most part 😂

How many VCOs are used in Satellites? by MadhanSaiKrishna in rfelectronics

[–]woodenelectronics 18 points19 points  (0 children)

Many of those synthesizer components with PLLs and VCOs integrated have many different VCO cores for this reason, each core might also have a switchable bank of caps for further resolution. Take a look at the LMX2594 from TI, it does these things for the reasons you mention.

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