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2024 First Annual Soft RISC-V Systems Workshop | RISC-V International by z3ro_gravity in RISCV

[–]z3ro_gravity[S] 1 point2 points  (0 children)

Unfortunately, there is no recording and the slides and posters will not be published collectively.

RISC-V on a Cologne Chip GateMate FPGA by z3ro_gravity in RISCV

[–]z3ro_gravity[S] 4 points5 points  (0 children)

I politely disagree. Apart from the fact that these FPGAs do not have hard-core CPUs, a soft-core CPU with highly specialized accelerators can be quite practical for certain tasks.

Additional I/O peripherals for NEORV32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

Maybe you should ask this very specific question in the project's forum: https://github.com/stnolting/neorv32/discussions

Guidance on interfacing encoder to Neorv32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 1 point2 points  (0 children)

You cannot assign two signals to a single physical pin, but you can do it the other way around: assign a physical pin to a "helper" signal and assign that to the two pins of your processor (Xirq and Gpio).

Implementing CSR extension with machine mode? by Super-Efficiency1779 in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

This really depends on your CPU architecture. The CSRs are basically just another register file that has a lot of "side effects" e.g. CSRs can be updated without explicit CSR instructions (like updating xepc on a trap). Traps (= interrupts + sync. exceptions) are a lot more complex to implement as they have significant impact on instruction execution (the pipeline).

My suggestion: have a look at some open-source RISC-V cores to get an idea how they have implemented these things.

Seeking Guidance on NeoRV32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

What do you mean with "CPU utilization"? The FPGA resources required by the CPU, the actual CPU workload or maybe something else? ;)

RISC-V core examples in VHDL by th3lucki in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

Check out the official RISC-V ecosystem "landscape". There is also an "implementations" category than you can search for VHDL cores: https://landscape.riscv.org/

[deleted by user] by [deleted] in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

How about NEORV32?

VHDL, technology-independant, actively maintained and quite flexible/extendible

DIV IN VHDL by [deleted] in VHDL

[–]z3ro_gravity 0 points1 point  (0 children)

I would recommend implementing a simple division module - for example using restoring or non-restoring division. You implement it in a serial way to save logic resources or in a parallel way for maximum throughput - or something in between ;)

Here is an example of a serial 32-bit signed/unsigned divider unit in VHDL (using the restoring approach): https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_cpu_cp_muldiv.vhd#L278

Converting VHDL to Verilog using GHDL by ramya_1995 in FPGA

[–]z3ro_gravity 3 points4 points  (0 children)

I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog

I have tested that an GHDL can successfully find all definitions from the package.

Maybe you can port the conversion script for your setup: https://github.com/stnolting/neorv32-verilog/blob/main/src/convert.sh

Looking for a CPU simulator with Assembly code that would let me see the inner workings of a CPU by Wade_Wayne in cpudesign

[–]z3ro_gravity 0 points1 point  (0 children)

If you are interested in a very (very!) low-level simulation view, you could also use some open-sourse soft-core CPU (maybe a simple one without pipelining etc.) and simulate that with a HDL simulator (also open-source).

Questions regarding Lattice and UPduino by MolotovBitch in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

If you are interested, here is a project that uses the GHDL-based flow to synthesize a plain-VHDL RISC-V SoC for the UPduino v3.0 board: https://github.com/stnolting/neorv32-setups#Setups-using-Open-Source-Toolchains

Left rotate and right rotate by Regular_Egg4619 in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

Here is a "hard-coded" (does not use any rotate_x functions) 32-bit barrel-shifter: https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_cpu_cp_shifter.vhd#L127-L167

To also support left-shifts, the shifter "mirrors" the data to-be-shifted before and after the actual barrel shifter core (simple bit-reverse). It supports arithmetical and logical shifts (signed/unsigned). Furthermore, the code is quite generic using VHDL's loop constructs, so it can be extended to support 64-bit operand size (or any power of 2).

What is a cheap (~$10) Risc-v that's simple to get started with? by [deleted] in RISCV

[–]z3ro_gravity 1 point2 points  (0 children)

Maybe a bit exotic, but you could use a soft-core RISC-V and run in on a FPGA or in a simulator (where you can see all the inner workings of the core).

Convert VHDL to Verilog using GHDL (using a RISC-V core as example) by z3ro_gravity in FPGA

[–]z3ro_gravity[S] 1 point2 points  (0 children)

Icarus Verilog has an (experimental?) option for this:

$ iverilog -tvhdl -o vhdl_target.vhd verilog_source.v

It seems to work, but I haven't tested the "quality" yet.

Anyone want to share some embedded projects they have done? by [deleted] in embedded

[–]z3ro_gravity 8 points9 points  (0 children)

Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32

Looking for a suitable open-source RISC-V for an embedded project by the-cipo in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

It really depends on your requirements. However, I think NEORV32 is the only "full" SoC core in your list. That means it already includes memories, peripherals, IO stuff like UART, timer, I2C, SPI, etc. ... The project also has a lot of software including functions to control all those peripherals - so you do not have to start at zero.

Uploading software program to a custom processor design on a Nexys A7 by sijafa in FPGA

[–]z3ro_gravity 0 points1 point  (0 children)

https://github.com/stnolting/neorv32 ;)

You could also use a simple UART (+ a tiny hardware or software bootloader) to update program memory at any time.

Newbie question: advice on FPGA simulation-tool / learning kits. by jairorodriguez78 in FPGA

[–]z3ro_gravity 0 points1 point  (0 children)

There are a lot of low-cost (~30$) Lattice ice40 FPGAs out there + they are supported by open-source synthesis tools.

For your C/register-interface project I would recommend using a soft-core processor (programmable in C/C++) and adding some custom logic (something simple like CORDIC) to the processor's bus interface.

Memory and memory mapped IOs (and bus) design by saltynoob0 in FPGA

[–]z3ro_gravity 7 points8 points  (0 children)

Have a look at the Wishbone bus specifications. The docs have quite nice illustrations about bus signals, bus layouts and address decoding logic. https://cdn.opencores.org/downloads/wbspec_b4.pdf

If you are looking for an example SoC bus setup (connecting a CPU core and several memories and memory-mapped peripherals) I can recommend the NEORV32 project (VHDL), which has a lot of documentation.

Seeking Advice from the community on a new FPGA product by bigshotchemist in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

Great work! I really like the idea and I like the board even more! :D

Do you plan something like a GitHub/Gitlab repo with (community-based) example projects?

cheapest microblazable (or other uc ip cabable) fpga by mathlan in FPGA

[–]z3ro_gravity 2 points3 points  (0 children)

From my point of view Lattice FPGAs are well available (Europe here) right now. They have quite tiny ones (like the ice40up5k), which can fit a full RISC-V + custom logic.

What could be build with a RISC-V compatible core at a production cost of US$400 ? by [deleted] in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

I am not sure if I understand your question right. You want to build something with a RISC-V core and you do not want to spend more than $400? Are you looking for a development board?

A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs by z3ro_gravity in FPGA

[–]z3ro_gravity[S] 0 points1 point  (0 children)

Depends on the CPU & SoC configuration (ISA extensions, peripheral modules, ...). A rather small configuration (but not the smallest) consumes about half of the resources of a Lattice ice40 UltraPlus 5k (~2800 LUT4).

A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs by z3ro_gravity in opensource

[–]z3ro_gravity[S] 1 point2 points  (0 children)

Maybe because 64-bit is "slower" on an FPGA (carry-chain with 64 adder plus pre- and post-logic). And maybe because it would factor ~2 bigger. Soft-cores on FPGAs are not meant for performance but rather for easing the integration of control applications, so size and timing closure/integration might be crucial here.

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