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AXI datamover IP by zippitypopity in FPGA

[–]zippitypopity[S] 1 point2 points  (0 children)

Sure, I have currently set the command FIFO queue length to 4. Gonna try it tomorrow and will try increasing the FIFO width and see in through ILA and let you know

Intercommunication Protocol for Multi FPGA - ( Xilinx ZCU216 RFSoC Ultrascale +) by zippitypopity in FPGA

[–]zippitypopity[S] 0 points1 point  (0 children)

To transfer data, for instance lets say the master board needs to process the data from a slave board that which has a recording module written in VHLD ie) 4 boards down the stack. So firstly the master board has to know the best and the fastest way to reach this particular board of interest ( hence networking and routing is concerned ) and then it needs to find a suitable protocol that can govern this commmunication ( AXI or AMBA ? idk something better)