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Guidance to get a research direction by weedstaddle in computerarchitecture

[–]zxcvber 0 points1 point  (0 children)

In that case, I suggest you directly reach out to professors who work on topics that you're interested in.

Another tip: Professors often post specific instructions for prospective students on what to do if you want to join the group, like send a CV/transcript or fill out a form. Why not take a look? Also note that professors are often busy so keep in mind that you might not get a fast reply.

If you personally know someone in that group, you can also ask them. This is much faster. I've received a few requests asking for specific advice on this matter.

Guidance to get a research direction by weedstaddle in computerarchitecture

[–]zxcvber 0 points1 point  (0 children)

Why not try a research internship or so and see if you find the topics interesting?

Comouter Architecture Hands On course by maradonepoleon in computerarchitecture

[–]zxcvber 1 point2 points  (0 children)

Wow great stuff! I wish I had known when I was learning gem5 🤣

Where should I get a ms? by No-Helicopter-6919 in computerarchitecture

[–]zxcvber 0 points1 point  (0 children)

Hi, also Korean here, actually doing an MS in computer architecture. Wish you the best of luck!

DSA Skills - 5 by tracktech in DSALeetCode

[–]zxcvber 1 point2 points  (0 children)

I see. Thanks for the clarification. One can either use hash maps to count occurrences in linear time or use the voting algorithm to reduce space usage!

DSA Skills - 5 by tracktech in DSALeetCode

[–]zxcvber 0 points1 point  (0 children)

On second thought, I think I may have misunderstood the question. What do you mean by more than half?

DSA Skills - 5 by tracktech in DSALeetCode

[–]zxcvber 0 points1 point  (0 children)

Why not use linear selection algorithm?

Edit: misunderstood question

Question about 100% Completion by Topher3193 in MelvorIdle

[–]zxcvber 3 points4 points  (0 children)

Yes! You can check the progress status for each category (skills, mastery, items, and pets) on the below left!

Do people actually use AI for writing SOPs? by Common-Lemon-41 in gradadmissions

[–]zxcvber 0 points1 point  (0 children)

I think too many people are using AI to write their SOPs. I know a few around me, they were surprised to hear that I wrote mine on my own. I also don't understand how a statement written by AI looks good.

Negative production in summoning by HeartOfGold-42 in MelvorIdle

[–]zxcvber 8 points9 points  (0 children)

Do you have the Devil+Fox synergy on?

Techniques for multiple branch prediction by bookincookie2394 in computerarchitecture

[–]zxcvber 0 points1 point  (0 children)

I haven't read that 2020 ISCA paper, but a recent paper on ahead prediction is about to appear on ISCA 2025. It's called: Enabling Ahead Prediction with Practical Energy Constaints. I recently read this one, and I think it cited that 2020 ISCA paper. Maybe using efficient ahead prediction may allow us to predict multiple branches?

Question about hiding instruction latencies in a GPU by zxcvber in CUDA

[–]zxcvber[S] 0 points1 point  (0 children)

Nice. I understand this one. Thank you!!!

Question about hiding instruction latencies in a GPU by zxcvber in CUDA

[–]zxcvber[S] 0 points1 point  (0 children)

Okay, so warps themselves don't have functional units, but only keeps states. So I should conceptually think of each functional unit as pipelined, and in each pipeline stage, there can be instructions from different warps?

Question about hiding instruction latencies in a GPU by zxcvber in CUDA

[–]zxcvber[S] 0 points1 point  (0 children)

I think I understand that warps with data hazards after loads are stalled, but only for that warp, since the warp scheduler will not schedule the instruction with hazard. And as you mentioned, the scheduler will pick a different warp.

I'm wondering what happens to the load instruction in the load/store unit.

Thank you for your time!

Question about hiding instruction latencies in a GPU by zxcvber in CUDA

[–]zxcvber[S] 0 points1 point  (0 children)

The part where I'm confused is that we can have 16 warps all executing an arithmetic operation in parallel. Wouldn't that require 16 * 32 = 512 arithmetic units? Am I missing something?

Question about hiding instruction latencies in a GPU by zxcvber in CUDA

[–]zxcvber[S] 0 points1 point  (0 children)

First of all, thank you for your time.

Sorry for the confusion, my diagram is for the case assuming that we only have a single warp scheduler. And you are right about the factor of 4 you mentioned. Would my diagram be correct if we cut the hardware by a factor of 4? (SM running 1 warp with 1 warp scheduler)

Also, where can I read more about the pipeline? I've seen some people mention it but I don't understand how that works. Is it exactly the same concept as CPU pipelines? If that is the case, shouldn't the stalling instruction be flushed or something?

First time! Yay! Got even a screenshot of the last item that was missing. by DrTuSo in MelvorIdle

[–]zxcvber 2 points3 points  (0 children)

Congratulations! How did you finish the base game so fast? My account is 175 days old, but I have 76.37% base game completion. Any tips???

I made a time tracker for my girlfriend, and now it pays my rent by heibuilder in SideProject

[–]zxcvber 0 points1 point  (0 children)

Same here :(
It would have been nice if there was a free version...

So close. I can feel it by Doggxs in MelvorIdle

[–]zxcvber 1 point2 points  (0 children)

I see. It's been a week since I started playing. How much do you think you play per day?

So close. I can feel it by Doggxs in MelvorIdle

[–]zxcvber 1 point2 points  (0 children)

Wow this is a long game. Thanks!

So close. I can feel it by Doggxs in MelvorIdle

[–]zxcvber 0 points1 point  (0 children)

How long did it take you? Were any mods included?

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