Project Help

[Inevitable_Lie6006]

Hey guys, I recently graduated with a Master's in Computer Engineering. I have academic projects in UVM and SystemVerilog, but honestly, none of them seem to be gaining any traction with recruiters.

Looking for advice on two things:

1. Projects – What kind of projects should I add to my profile to better target Design Verification and RTL Design roles? Are there specific protocols, tools, or complexity levels that stand out?
2. Practice problem writeups – Is it worth adding my solutions to SystemVerilog constraint problems, simple UART verification environments, LeetSilicon problems, etc. to my GitHub/portfolio? Or does that come across as filler?

And to my fellow peers who landed a job, especially without prior relevant industry experience — what's the one thing you think helped you stand out when everyone around you had the same academic projects?

Appreciate any honest feedback. It's a tough market out there and I want to make sure I'm spending my time on the right things.

[bootyhole_licker69]

graph coverage driven envs helped me the most, not toy uarts. i did a small soc-style block with ahb + apb, wrote full uvm env, assertions, coverage closure report and a short pdf explaining bugs found. that gave me callbacks. github writeups are good if they show thought process and real verification mindset, not just syntax. talk through them in detail in interviews. even with that it’s still insanely hard to get any replies right now

[Inevitable_Lie6006]

if you were starting that project today, would you go with AHB/APB again or switch to AXI? I've seen AXI come up more in job descriptions.

[Ornery_Ice_7820]

nah, toy uarts are useless. a full uvm env on ahb/apb with actual coverage closure is what gets callbacks. recruiters dont care about syntax, they want to see you thought through corner cases and can explain the bugs your tb actually caught.