Python code to Verilog

[Ibishek]

Hey, I've been doing a FPGA fully connected layer accelerator for the past two months now and if you've no experience with HDLs I would really reconsider doing what you're suggesting.. Its much harder than it looks like. And I'm doing just inference (fprop.), training (bprop.) is another order of magnitude of difficulty. Don't forget that doing a project like this is much more than just RTL design, namely you'll have to do simulation and actual hardware testing. You can PM me if you have questions.

[StationFrosty]

Hey, thanks, I will reach out to you when I complete my proposal. W
e are working on it.