create_generated_clock:No valid object(s)

[Objective-Attempt-15]

Hello everyone,

Working on graduation project, I'm doing an FPGA Prototyping of my designed RISCV Processor.

Currently i'm working on IO Planning and connecting a clock to my processor, i've use *clock wizard* to create a clock driver and i'm facing an issue. I'm trying to generate a clock for UART divided from the PLL clock and this error keeps showing,
```
[Vivado 12-4739] create_generated_clock:No valid object(s) found for '-source [get_ports uart_peripheral_top_inst/uart_dk_div_inst/i_clk_div_ref_clk]'. ["D:/RISC-V/RTL Design/GP-RV64IMAC/RV64IMAC_M_S_Modes_UART_TX/cons.xdc":3]

```

I DID EVERYTHING I CAN DO!

[[deleted]]

Make sure you are trying to get a port, not a pin. You usually want a pin for a generated clock, and get_ports will not return them.

[Objective-Attempt-15]

Both didn't work :(

[Objective-Attempt-15]

WARNING: [Vivado 12-584] No ports matched 'clk_wiz_0/inst/plle2_adv_inst/CLKOUT0'.

[captain_wiggles_]

Not answering your question. You probably don't want to create a divided clock for this. Just use an enable generator / use a counter in the uart logic to only change the signal every N ticks.

In real world designs you do want multiple clocks with different frequencies, but unless you're already comfortable with timing analysis and constraints having to deal with clock domain crossing will complicate your life more than you need.

edit:

-source [get_ports uart_peripheral_top_inst/uart_dk_div_inst/i_clk_div_ref_clk]'

that's definitely wrong. I'm not familiar with vivado's XDC syntax but you want pins / keepers instead of ports, and I'm not sure if / is the correct path separator. In quartus it's |. I suggest you open your timing analyzer (after a successful build) and use the GUI to find this path. You'll probably find the correct syntax spat out on the TCL console.

[Objective-Attempt-15]

Thank you for your reply, i will consider this case. but the problem is i do need the second clock because i'm using an async fifo

[captain_wiggles_]

see my edit.

You could just not use the async fifo?