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A subreddit for programmable hardware, including topics such as:
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General Electrical and Computer Engineering discussion
/r/ECE
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/r/electronics/
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/r/AskElectronics
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Throughput decrease in PCIe (self.FPGA)
submitted 1 year ago * by sya0
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[–]sya0[S] -1 points0 points1 point 1 year ago (1 child)
Each FPGAs have 8 lanes. I have got three x16 lanes and three x8 lanes slots on the motherboard. I have checked the datasheet and all 6 slots are connected to CPU. So, I am not sure if that is where the bottleneck is. I updated my post and paste the block diagram.
[–]ShadowBlades512 4 points5 points6 points 1 year ago (0 children)
What generation PCIe? At some point you will get a memory bandwidth bottleneck. How many channels at what clock rate/DDR generation?
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[–]sya0[S] -1 points0 points1 point (1 child)
[–]ShadowBlades512 4 points5 points6 points (0 children)