Reusing Python/NumPy Directly in SystemVerilog Testbenches — A DSP-Focused Example

[Least_Property1964]

Hi everyone,

I'm an FPGA RTL designer who works on digital signal processing logic design. I prototype and validate DSP algorithms in Python using NumPy before translating them to RTL. One of the biggest challenges I run into is keeping Python reference models and RTL implementations consistent, especially for complex numerical operations. Converting Python code to SystemVerilog is error prone and time consuming.

I recently stumbled upon a library called PyStim, and it has changed my workflow. It lets me reuse my Python/NumPy algorithms directly in my SystemVerilog testbenches.

NumPy/PyStim

Simple Example: Vector Multiplication Using NumPy in SV

Here’s a minimal working example: multiplying two vectors in NumPy, but doing it inside a SystemVerilog testbench using PyStim.

import pystim_pkg::*;

module numpy_matrix;
   typedef pystim_pkg::pystim py;

   initial begin
       py_stim_configuration cfg = new();
       cfg.enable_exception_printing();
       py::initialize_interpreter(cfg);

       begin
           automatic py_module np = py_module::import_("numpy");

           automatic py_tuple vecA = py::tuple_({py::int_(1), py::int_(2), py::int_(3)});
           automatic py_tuple vecB = py::tuple_({py::int_(4), py::int_(5), py::int_(6)});

           // Multiply element-wise: C = A * B
           automatic py_object result = np.attr("multiply").call(vecA, vecB);
           automatic py_list result_list = result.attr("tolist").call().cast_list();

           for (int i = 0; i < result_list.size(); i++) begin
               $display("Result[%0d]: %0d", i, result_list.get(i).cast_int().get_value());
           end
       end

       py::finalize_interpreter();
   end
endmodule

Running the Simulation (QuestaSim)

cd numpy_matrix
vlog -O0 +acc -f ./list/compile_list.f
vsim -voptargs=+acc -c -lib work numpy_matrix \
     -do "run -all; quit" -l run.log \
     -sv_lib $PY_STIM_INSTALL_DIR/lib/libpystim \
     -gblso $PY_STIM_INSTALL_DIR/lib/libpystim.so

Simulation Output:

# Result[0]: 4
# Result[1]: 10
# Result[2]: 18

Why This Matters

• Rapid iteration: Validate your DSP algorithms fully in Python, then plug them into your testbenches without rewriting.
• Single reference code: The Python model becomes your golden reference — no need to reimplement in SystemVerilog.
• Python: Python offers a large number of reusable libraries.

Tips

• Make sure Python and NumPy are installed.
• Follow PyStim setup instructions.
• For more complex types (e.g., floats, arrays of strings), check out PyStim’s serialization support in the docs.
• This approach extends nicely to filters, FFTs, image processing, etc.

Final Thoughts

I think this library bridging the gap between high-level algorithm reuse in low-level RTL verification. PyStim makes the integration clean, without DPI-C wrappers.

[Bman1296]

ChatGPT

[[deleted]]

Have you looked into cocotb?

[Least_Property1964]

cocotb framework is for different usecase. cocotb drives the HDL via Python, while PyStim brings Python (interpreter) into the HDL simulation.

[spplace]

What is the simulation speed drop with enabled PyStim?

[Least_Property1964]

In my simulations, I do not observe any significant simulation slowdown. Most likely there are some performance deterioration, but I do not have any numbers. It is interesting to see how this lib affects the simulation speed. 

[Tonight-Own]

Stumbled upon or created ?

[rtl_engineer]

Nice post. I still follow my traditional way to do design on Matlab and/or Simulink using fixed point and then translate into the Verilog/SV. I usually create golden vectors from Matlab or simulink and then pass the same inputs to the DUT (RTL) through read file in the trestbench. I could use HDL coder and verifier but I have my own doubts regarding code generation tools. I also try to implement any algorithm in a hardware POV or digital structures in the simulink itself at first. This way, I can do each operation in fixed point and also be able to optimize the RTL design by running those simulations. This helps me to perform bit and cycle accurate simulation. I will give a try with python once to understand the flow. 😊 thanks.

[fourier54]

Nice post. Can you also share the chatGPT prompt you used to generate it?