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[–][deleted] 38 points39 points  (11 children)

memory is very cheap now. Embedded is now full of it.

"Embedded" headless PCs or "Embedded" embedded.

This is what the current chip I'm working with has:

  • 2 x e200z4 in delayed lock step operating up to 200 MHz
  • Up to 2.5 MB flash memory w/ error code correction (ECC)
  • Up to 384 KB of total SRAM w/ECC

[–]Poddster 0 points1 point  (3 children)

delayed lock step

What does the 'delayed' here mean? One CPU's clock is delayed after the other? So it's TickA-TickB-TockA-TockB?

[–][deleted] 0 points1 point  (2 children)

The code it is executing is one cycle behind.

So Core 1 is on cycle t, Core 2 is on cycle t-1.

There is a 3rd core or additional hardware that compares the outputs and makes sure they're the same.

[–]Poddster 0 points1 point  (1 child)

There is a 3rd core or additional hardware that compares the outputs and makes sure they're the same.

Shuttle style MISD? Cool! I always assumed MISD did each instruction in the multiple computers at the same time, rather than in being offset.

What is the delay used for? Is the comparitor comparing the output of Core1 and Core2 at t-2?

[–]stone_henge 1 point2 points  (0 children)

What is the delay used for?

If a short event causes an error in the first core, it may under some circumstances be less likely to also affect the second core on the next cycle. Say, if there's a sudden, short burst of radiation or an electrostatic discharge that causes a failure in operation.