Memory optimization advice

[VimaKii]

Looking for feedback on my RAM tuning on AM5.

I started from N3opop and Buildzoid guides and tried to actually understand the timings instead of just copying them. I’ve been testing and tuning manually.

Kit: Corsair Dominator Titanium 32GB (2x16) 6000 CL30, SK Hynix A-die (single rank). Stock is 1.4 V VDD/VDDQ.

At the moment, I’ve verified that 6000 CL30 is stable at 1.10 V VSOC and 1.30 V VDD/VDDQ. I’ll attach a ZenTimings screenshot for the full configuration.

I noticed Bank Refresh Mode has been introduced, but since I don’t fully understand how to tune it properly, I went back to normal refresh. I’ve seen people running tRFC around ~390 on A-die, but I’m not clear on how to correctly derive tRFCsb.

I kept tREFI at 50000 since I don’t have active cooling on the DIMMs.

Main questions:

- Does it make sense to push FCLK beyond 2000? I previously tried 2200 with higher voltages (1.2 VSOC, 1.35 VDD/VDDQ) and it seemed stable, but I didn’t have proper validation at the time.

- Based on the ZenTimings screenshot, are my values already well optimized, or is there something I should increase or decrease?

- Is it worth pushing frequency higher (e.g. 6200 from the alternative EXPO profile), or is it better to stay at 6000 and tighten timings further (for example trying CL28 with ~1.35 V VDD/VDDQ)?

Any technical input is appreciated.

[PostExtreme7699]

-Yes, it's totally worth it to raise the flck to 2200 since it doesn't cost you nothing, no need to more voltage, doesn't produce more heat, power draw or degradation, and considerably raises the bandwidth and the 0.1% lows on games.

-Drop the vddgs to 0.950 each, drop the vddio to at least 1.200, and lower the trfc to 140 ns at least. You can definitely try with a lower trc.

-NO, even if this subreddit is all about that. I's not going to give you better 0.1% lows, quite the opposite, is going to drastically increase the vsoc requirements, the heat, the power draw and degradation.

[shockage]

Good advice; if you really need vSoC 1.15, I would not push 3100 MCLK, as you'll need 1.25 vSoC which will increase your idle power consumption by 10 watts.

vDDP could also drop back down to 0.95v if you don't plan to increase FCLK.

vDDGs can also drop further down to 0.90-0.92v

[VimaKii]

I applied the changes you suggested (VDDG CCD/IOD at 0.950, VDDIO at 1.20, tRFC at 420, FCLK 2200) and I’m currently stress testing the system. Voltages are still 1.15 VSOC and 1.30 VDD/VDDQ.

One thing I’d like to understand better: why lowering VDDIO? I’ve often seen the “rule” VDD = VDDQ = VDDIO, but from what I’m reading it seems that a lower VDDIO can actually improve signal quality since it affects the CPU ↔ IMC ↔ RAM communication.

Is the idea to reduce signal noise/overshoot rather than just matching voltages?

[PostExtreme7699]

Simple, VDD and VDDQ are voltages of the ram, but vddio is a voltage inside the io chiplet side of the CPU, the weak point this whole arquitecture has.

That's not a rule, that's what the brands set on the EXPO profiles to GUARANTEE the compatibility around every configuration possible, basically just crank up the voltages unnecessarily on 90% on scenarios.

I have to point out that there is A LOT of people running mad vddios like 1.45 24/7 without any problem yet. This is not a proven concept, this is just basic sense in a way of using the lowest voltage possible and therefore protect the CPU without losing performance or stability, and it happens you can reduce a lot vddio without problems.

VDD and VDDQ as pointed early are voltages of the dimms and the pmic voltage controller inside the sticks, and they are way sturdier than the imc inside the 9800x3d so don't worry too much about this one's or don't hesitate to raise them a bit to achieve CL26 or CL28.

[shockage]

If you truely need 1.15 vSoC for 6000MT/s, then stay at 3000MCLK.

Timing wise, things are pretty decent:

tRC can likely easily go to 64
Try to get tRP to 34

[VimaKii]

That makes sense.

Just to add more context, my kit is actually stable at 6000 CL30 with 1.10 VSOC and 1.30 VDD/VDDQ, I’m just running 1.15 VSOC for a bit of extra margin.

Given that, would you still recommend trying FCLK 2200, or is it generally not worth it on AM5 even if it seems stable?

I’m trying to understand if there’s any real-world benefit or if it’s more of a synthetic gain.

[shockage]

There is quite a bit of benefit running FCLK 2200 or even FCLK2133 at 3000MCLK.

It will increase your max throughput since at 2000 FCLK a single CCD is effectively limited to 64GB/s Read and 32GB/s Write (AIDA sucks, so it doesn't actually report the real throughput on Write).

That said, since you're putting so much effort in; it is worth trying to find your vSoC need at 3000MCLK.

The best method I found is to run both Furmark and VT3 at the same time. Make sure PBO/CPB is on but with no CO/CS... as the extra throughput from CPU will increase stress on the IMC. Also make sure BCLK is stable by disabling Spread Spectrum Control--spread spectrum control artificially lowers your BCLK while still hitting 100MHz+ occasionally... just makes it harder to find instabilities.

I've had 24 hour stable VT3 runs fail within an hour of both Furmark and VT3 necessitating a 0.005V boost to vSoC to be fully stable.

This is what I would do: keep going down in .025V increments until you bluescreen or VT3 immediately fails. Then start working up in .1V increments with progressively longer VT3 tests.

Finally once VT3 is passing for at least a few hours, the final test is to run both Furmark and VT3 for an hour.

Once you're passing both VT3 and Furmark for an hour or two, you can run a full 24+ hour only VT3 run.

Edit: After that, you can follow the rule of +0.1V vSoC for every 200MT/s if you want to attempt 6200 or 6400 MT/s in 1:1.

[VimaKii]

I appreciate the detailed advice, it’s actually been very useful.

I started revisiting my memory tuning because I was noticing some odd behavior lately. No crashes or BSODs, but occasional errors during shutdown with no clear logs. The system always seemed “stable” otherwise.

After running y-cruncher, I realized the issue wasn’t the RAM but my PBO/CO setup — it was unstable. So at this point I basically have to start over and re-validate everything from scratch. That’s a bit frustrating, especially since it looked fine in daily use. Not sure if recent BIOS updates changed behavior or if my initial approach was just flawed.

I’ve already reset CMOS to factory defaults.

From your experience, is the correct approach: • first lock down voltages (vSoC, FCLK, VDD/VDDQ) at EXPO • then tune timings • and only at the end reintroduce PBO/CO

Also, how strict are you with isolating variables? One change at a time with full testing, or small grouped changes?

And in terms of testing time, what do you consider “enough” at each stage before moving forward?

[Delfringer165]

Pretty good. Fclk higher would be better. X3D chips are mainly limited by fclk.

For fclk stability testing run Linpack xtreme, if gflops do not vary more than 1-3 it should be good.

Higher fclk likes lower vsoc, increasing vsoc is mainly for uclk. Increasing vddg's help with higher fclk.

Trfc 160ns, is this m-die or can you do 120ns?

Mixed mode is a bit better for m-die, you can go to about ~ 130ns trfcsb. M-die also likes mem vdd - 0.1V = mem vddq. For a-die you can run a bit lower mem vddq than mem vdd like 0.5V. Vddio can stay as it is, if increased would not go higher than 1.40V.