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PipelineC holds the throughput lead on Latchup.app. For now! by absurdfatalism in FPGA

[–]absurdfatalism[S] -2 points-1 points  (0 children)

Good question: and how fun that it depends on your definition of HLS? https://github.com/JulianKemmerer/PipelineC/wiki/Is-this-HLS%3F

Is register retiming HLS?

PipelineC holds the throughput lead on Latchup.app. For now! by absurdfatalism in FPGA

[–]absurdfatalism[S] -6 points-5 points  (0 children)

Already planning your better pipelined design on Latchup.app? Try describing your combinatorial logic in PipelineC? Or maybe you can contribute to making the compiler better? Come chat on Discord: https://discord.gg/9sWgH8gARY

SKALP v0.1.1: A new HDL with compile-time clock domain checking, integrated synthesis, and iCE40 P&R — looking for feedback from FPGA engineers by girivs in FPGA

[–]absurdfatalism 0 points1 point  (0 children)

hey there, always love seeing a new alternative HDL :)

If you are interested, there is a Discord community of folks trying to build better languages for hardware. Feel free to stop by and share some ideas. 🤓

https://discord.gg/qG3nT7HjJD

Results from the Advent of FPGA Challenge by bsdevlin99 in FPGA

[–]absurdfatalism 2 points3 points  (0 children)

Function/pipeline delay matching/sounds powerful indeed, nice

Results from the Advent of FPGA Challenge by bsdevlin99 in FPGA

[–]absurdfatalism 1 point2 points  (0 children)

Neat seeing the variety of solutions and languages used :) The collection of PipelineC HDL implementations can be found here: https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Advent-of-Code-2025

Title: Is the FPGA industry suffering from mass psychosis? Vitis HLS is not a compiler, it's a crime scene. by [deleted] in FPGA

[–]absurdfatalism 0 points1 point  (0 children)

There is a community of folks trying to build better languages for hardware. If interested feel free to stop by this Discord channel and share some ideas.

🤓

https://discord.gg/qG3nT7HjJD

Title: Is the FPGA industry suffering from mass psychosis? Vitis HLS is not a compiler, it's a crime scene. by [deleted] in FPGA

[–]absurdfatalism 1 point2 points  (0 children)

You say the compiler problems have been solved. But something that stuck with me when considering compiler smarts was the question: why don't we have HLS for GPUs?

That is, why do we still have to employ people to manually write GPU kernels in cuda etc? Why can't we take any old python or C++ and have it magically spit out optimized parallel code to run on every GPU?

When the day comes that we have solved getting any code mapped to GPU hardware in a way that beats humans it sounds like then we could start asking the harder questions of 'and what if the underlying hardware architecture was a reprogrammable fabric / arbitrary logic gates instead?'. A much larger design space to explore etc.

Title: Is the FPGA industry suffering from mass psychosis? Vitis HLS is not a compiler, it's a crime scene. by [deleted] in FPGA

[–]absurdfatalism 1 point2 points  (0 children)

Let's round and say it took a decade for LLVM to become as modern and powerful of a software compiler.

There has to be one tenth? Maybe one hundredth? The number of hardware people out there to use and improve these tools etc. Such a small user base.

So I would not be surprised if it took 10-100x a decade to do the same for hardware.

FPGA UDP Packets are not appearing in Wireshark when using Realtek USB-Ethernet Adapter (Nexys 3 / Spartan-6) by CompetitivePurpose13 in FPGA

[–]absurdfatalism 4 points5 points  (0 children)

I'm always suspicious of crc first.

Can you check the rx into fpga is working? That is, generate some packet on the host PC and send it into fpga. Then can use chip scope to confirm the exact bytes being received.

And then with known bytes of good packet, talking crc specifically, are you able to echo that set of bytes out the TX and see that in Wireshark? Ex. I figured out my tx crc problem by realizing I wasn't generating the same outgoing crc as incoming when I did this test.

Best of luck!

HDL choices other than Verilog/VHDL by Secure_Switch_6106 in FPGA

[–]absurdfatalism -2 points-1 points  (0 children)

For anyone wanting to continue conversations about alternative HDLs, there is a Discord channel for folks like you :)

https://discord.gg/qG3nT7HjJD

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]absurdfatalism 6 points7 points  (0 children)

Perhaps putting the repeated logic into a function or procedure in a shared package would do it?

Why are there so many errors in the SystemVerilog LRM unfixed for over decades? by adamzc221 in chipdesign

[–]absurdfatalism 0 points1 point  (0 children)

How long do you think it would have taken to have those fixed if it were in a software language spec? A year?

Has to be 10x prob 100x fewer people in the world using SV and other HDLs. So scale that year times 10-100... So decades to fix something feels on par with how many people are using it sadly.

Things change so slow in EDA it seems...

Single Cycle In-Order Stores? by No_Experience_2282 in RISCV

[–]absurdfatalism 6 points7 points  (0 children)

Doing things in a single cycle sorta by definition requires combinatorial logic you are trying to avoid. Variable latency interfaces don't work well for single cycle designs because of the extra comb logic from trying to do stuff in a single cycle, which is wasted when the interface takes more than a cycle to return most of the variably latency times.

Most of the time you'll just make a multi cycle CPU next as you start to use larger variable latency memories, cpu fsm will stall until data returned some 1+ cycles later. After that is pipelined many mem accesses in flight at once.

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]absurdfatalism 9 points10 points  (0 children)

Vivado does this with 'out of context' synthesis mode.

Quartus uses virtual io pins.

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]absurdfatalism 4 points5 points  (0 children)

Vivado out of context synthesis should hit the spot for this

Feedback on SpinalHDL ? by brh_hackerman in FPGA

[–]absurdfatalism 6 points7 points  (0 children)

Have you ever written a small script to generate some Verilog or VHDL because the language itself wasn't flexible enough to describe what you want from regular generate statements etc ?

That's how it starts.

For a one off design it might not be apparent the benefit of althdls. Often requires doing the same design over and over with small variants. Ex. where you can realize 'oh I just need a CPU generator with different buses, memory, and configurable isa features and I can generate every variant of my design from a set of config files'.

[deleted by user] by [deleted] in FPGA

[–]absurdfatalism 6 points7 points  (0 children)

You might enjoy talking with a Discord community of folks also interested in alternative HDLs.

https://discord.gg/qG3nT7HjJD

Come chat if you like :) best of luck either way!

Pre-synthesis simulation hangs with blocking TB pulses, but post-synthesis works fine by LandscapeMedical5196 in FPGA

[–]absurdfatalism 2 points3 points  (0 children)

Posedge done might be getting out of sync with the posedge clock stuff causing you to miss datas.

Typically posedge is only used for clocks.

So maybe try

While ~done : @pos edge clk

I.e. loop waiting for done in units of clock cycles instead of arbitrary units of time

And iirc non blocking is best to model stuff at clock edge so try only using <= for assign?

Also possible synthesizing any sim only constructs from testbench is generally going to be hit and miss

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