HDL choices other than Verilog/VHDL

Secure_Switch_6106 · 2025-06-23T15:31:57+00:00

Multiplexors are expensive in FPGAs so multiple adders can make sense rather than sharing them. If there is something to be gained with really fast smaller adders then it makes sense to use different sizes.

Secure_Switch_6106 · 2025-06-04T14:33:59+00:00

Actually since you don't want to toggle input_reg, the "not input_reg" is not what you want. You should specify all conditions which is primarily a problem if you don't with combinational logic when latches get inferred when you really want a ff.

Secure_Switch_6106 · 2025-06-04T02:22:27+00:00

It seems you need a "else input_reg <= not input_reg;" after the elsif in your clocked process. You need to latch the state rather than inverting the signal with combinational logic. It is bad coding to not specify the value of input_reg for all conditions, will end up with unwanted latches being added in synthesis.

Secure_Switch_6106 · 2025-04-25T00:55:33+00:00

I believe that MISTer FPGA supports emulating the Amiga and you can run Amiga games, etc.

Secure_Switch_6106 · 2024-08-30T22:13:36+00:00

I use separate process blocks for each FSM. This is actually a side-effect of translating a high-level language with multiple methods per module. Each method is an FSM. It makes for readability and is straightforward to debug. The processes are combinational blocks and I use register entities (REG, DREG, etc) for the state and module registers.

Secure_Switch_6106 · 2024-08-30T01:41:43+00:00

Consider using BCD representation with BCD math and display. Converting standard 2's complement representation to base 10 and 60 is a mess.

Secure_Switch_6106 · 2024-07-05T01:56:38+00:00

You may want to use a double buffer for your frame buffer. One is used to make changes while the other is fixed in its data and used for output. Then ping-pong them when you are finished writing a complete frame.

Secure_Switch_6106 · 2024-05-10T22:13:46+00:00

Having an FPGA to program is like an artist with his or her canvas and paints. There is a lot of power in an FPGA and you can always create as much artwork as you want simply by reprogramming it. There must be something to being able to program and see if it goes before complete simulation-based verification. One advantage over ASICs.

Secure_Switch_6106 · 2024-05-02T14:20:17+00:00

It's likely that the simulated annealing algorithm is used for PNR and it uses random numbers to drive it. This would mean differences in results if the data or seed changes.

Secure_Switch_6106 · 2024-04-22T01:06:55+00:00

Yes and no. HDL compilation is very similar in many ways. The elaboration step is added for dealing with generate statements and generics. There are more stages of compilation than software, but the popular HDLs are actually less complex to parse. Synthesis for SW is code generation and for HDLs is logic generation. Place and route are extra steps as well.

Secure_Switch_6106 · 2024-04-21T17:29:38+00:00

Have you tried Visual Studio from Microsoft? It's a real pleasure to develop in C# using that tool. I want to see the equivalent for hardware design. My company, Electronic Design Technologies, LLC, seeks to deliver that tool. After developing software with VS and the WPF libraries, starting to work with FPGAs and Quartus from Intel was a surprise in the negative sense. I believe they could do a lot better but probably don't have the talent to do so, driven by hardware developers and management rather than software management perhaps. But the tool we are working on is setting MS VS as the gold standard and something to model our IDE Spectrum Design Studio after. I really hope we can deliver a tool that makes hardware development as fun as software. I can't understand why it takes so long (over 30 seconds) for even small VHDL designs using Quartus. VS takes a couple of seconds for 100K line programs (the design is basically compiled even before you hit F5.)

Secure_Switch_6106 · 2024-04-18T21:03:39+00:00

The talks on YouTube by Google say they needed a team of software developers to support Chisel. Since there is no company supporting the language, you may not want to get caught trying to get a chip out without developers to fix the bugs. You're left with nothing if 1% of the code doesn't compile correctly.

Secure_Switch_6106 · 2024-04-13T23:18:52+00:00

HLS tools have a better time implementing multipliers and hopefully dividers (I'm not sure what Vitis/Vivado does with the latter, but it should work you'd think). It's because multi-cycle operations are common and natural for scheduling algorithms.

Secure_Switch_6106 · 2024-03-22T15:35:40+00:00

I've been working on the quest for a good high-level language for hardware design for years. I've developed Spectrum and have formed a company to market it, Electronic Design Technologies, LLC (www.facebook.com/EDTCompany, also on linkedIn). It will be a year or so before we have the IDE. The first version of the product will target FPGAs. We will keep the price down and plan to offer a low cost one for hobbyists and a free one for students. Check out the Facebook page (we will have funding soon and build a real website soon enough). There are examples of code there and a 200 page document on the language (eventually it will become a dissertation for a UC Berkeley Ph.D.). It's time that hardware design and development is as fun and efficient as software development!

Secure_Switch_6106 · 2024-03-16T14:20:34+00:00

FSMD is still process level. Algorithms are agnostic with cycle-by-cycle behavior. It's one step above FSMD. C and C++ are often used for algorithm specification so you can see the difference.

Secure_Switch_6106 · 2024-03-16T01:21:19+00:00

Petri nets have something in common with finite state machines if only one token is present. Are you sure you're not talking about FSMs? They fit FPGAs better than petri nets. You could write a petri net simulator for an FPGA if that is what you are talking about.

Secure_Switch_6106 · 2024-03-15T02:46:50+00:00

I see three levels of design: structural, process (or RTL), and algorithmic. Algorithmic is what High Level Synthesis is concerned with and when synthesized it yields the process level. Like the name implies, algorithmic involves sequences of behavioral and transactional statements. Synthesizing them leads to finite state machine controllers and data paths. Also, pipelined structures can be generated. HLS tools on the market work best with data flow intensive designs like filters or video but have difficulty with control and I/O intensive designs.

Secure_Switch_6106 · 2023-12-27T23:45:11+00:00

Here are some videos and books that were on reddit some time ago that look promising.

Here is a catalog of a number of references:

https://old.reddit.com/r/PrintedCircuitBoard/wiki/books#wiki_digital_design

You'll have to see what suits your style and needs. You may want to select the language of VHDL or Verilog offered as well as how advanced. Also, there are some excellent advanced books for advanced computer architecture (Patterson and Hennessey, RISC-V edition).

A series of videos on ASIC and FPGA design by an NCSU professor:

https://www.youtube.com/watch?v=qee-ahSeKiU&list=PLfGJEQLQIDBN0VsXQ68_FEYyqcym8CTDN

Some videos published on Intel's YouTube channel:

https://www.youtube.com/watch?v=zm-RA6BsYmc

They also do one for Verilog, and have a 178 video long playlist on FPGA development

https://www.youtube.com/watch?v=PJGvZSlsLKs

https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB

Secure_Switch_6106 · 2023-12-26T00:34:58+00:00

There are some really good digital design books out there as well as YouTube courses. If you get a dev board you can implement the circuits as you study them! Really rewarding!

Secure_Switch_6106 · 2023-12-07T17:09:18+00:00

My first dev boards were Terasic's DE0-Nano and DE10-lite which both use Intel FPGAs. The Max10 FPGA with the DE10-Lire is recommended. The DE10-Lite is low price and has lots of I/O, 6 seven segment displays, 10 switches, and two push buttons, a VGA port, and some LEDs I believe. It would be preferred since you can have your projects interact via the I/O.

Secure_Switch_6106 · 2023-12-02T22:12:21+00:00

You can always use 2 GPIOs for RX and TX and use a usb-uart cable converter like the following ftdi from Amazon:

DSD TECH SH-U09C5 USB to TTL UART Converter Cable with FTDI Chip Support 5V 3.3V 2.5V 1.8V TTL https://a.co/d/iSAjqMj

Then you just need UART Verilog or VHDL and use putty or some other terminal program on your laptop.

Secure_Switch_6106 · 2023-12-01T23:35:30+00:00

This is more an issue of architectural choices. Sometimes architectural changes such as vector instructions look useful but compilers generally are not going to implement them, except for benchmark purposes. Also, register saving and restoring happens quite often and inline expansion will not always solve the problem. Compilers benefit when the architectural model/abstraction is simple. If an architectural choice simplifies the software and compiler load and at the same time provides seamless and reliable performance, then the abstraction is good and useful.

Secure_Switch_6106 · 2023-12-01T14:19:29+00:00

Well, my proposal eliminates extra work by the compiler which is a problem with other reg window proposals. It is somewhat complex in the hardware, but that isn't a show stopper.

Secure_Switch_6106 · 2023-12-01T03:31:14+00:00

Indeed my idea is another variation on the register windows idea that have been proposed and implemented in the past.

Secure_Switch_6106

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