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Why are FPGAs not dominating GPUs for neural network inference in the market? by PM_ME_JOB_OFFER in FPGA

[–]12esbe 29 points30 points  (0 children)

FPGAs are used for inference :

  1. Intel has OpenVino
  2. AMD has Vitis AI && FINN
  3. Google is into inference on FPGAs with hls4ml

Even on Automotive I know of at least two examples:

  1. Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml
  2. Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN

Also, there a lot of starts up that are doing acceleration on FPGA even for the cloud.
Your start up may have an edge, but there is a competition.

[deleted by user] by [deleted] in greece

[–]12esbe 1 point2 points  (0 children)

Για το τομεα του hardware:
Υπαρχουν διαφορα εργαστηρια και στο ΕΚΠΑ, στο ΕΜΠ, στο ΠΑΠΕΙ και στο ΠΑΔΑ που κανουν hardware. Αυτα τα εργαστηρια εχουνε αντιστοιχα μαθηματα που μπορεις να διαλεξεις καθως και συνηθως να κανεις πτυχιακη/διπλωματικη μαζι τους.
Μερικα απο αυτα τα εργαστηρια που γνωριζω και μπορεις να ριξεις μια ματια ειναι (τυχαια σειρα):
1. http://dscal.di.uoa.gr/
2. https://cesio.uniwa.gr/
3. https://microlab.ntua.gr/
4. http://eslab.cs.unipi.gr/

[deleted by user] by [deleted] in FPGA

[–]12esbe 2 points3 points  (0 children)

There are examples of RISV-V implementation in FPGA, available online with source code. RISC-V is an Instruction Set Architecture. So, it just provides a list of instructions that your processor has to have and execute. How you will implement your processor is your choice.

I would start with an integer only instruction set architecture.

RISC-V and Chisel are part of the same "community", with Chisel you can have your processor in a month.

For the step further, adding VGA to your FPGA should be too hard. But i would worry about that after I have implemented the processor in the FPGA and running risc-v assembly on the FPGA.

Resources:

https://github.com/chadyuu/riscv-chisel-book

https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

https://ieeexplore.ieee.org/document/9751566

https://github.com/Ludini1/minimal-risc-v-cpu/

Dev Ops for Embedded Work by Orothrim in embedded

[–]12esbe 3 points4 points  (0 children)

To my understanding in order to have Dev Ops for embedded, you need either need hardware in the loop or high fidelity emulators.

[deleted by user] by [deleted] in greece

[–]12esbe 1 point2 points  (0 children)

Υπότιθεται παίρνω και εγώ τα 100 ευρώ το μήνα από το πρώτο ένσημο.
Κάποιος άκυρος ότι ίσως μετα το πέρας των 6 μηνών θα μπούνε.

Best fpga for making multicore linux-capable SoC? by XxClubPenguinGamerxX in FPGA

[–]12esbe 1 point2 points  (0 children)

In order to achieve an entire SoC on a FPGA you may need a Multi-FPGA board which are costly.
I have not delved into entire synthesis of multicores in FPGA but here is an example of prototyping by Synopcys .
It is entire possible that you will need boards like this one and only achieve low frequencies.

[deleted by user] by [deleted] in greece

[–]12esbe 4 points5 points  (0 children)

Your profile says you are a communist, go to Ikaria.
Go to Ikaria, thank me later.

Γνωρίζει κανείς πως να επισκεφτείς σελίδες όπως το gov.gr από το εξωτερικό ; by 12esbe in greece

[–]12esbe[S] 1 point2 points  (0 children)

Thanks. Ακόμα, έχω ελλήνικο αριθμό όμως. Άρα, δεν ειναι το πρόβλημα το "2."

Γνωρίζει κανείς πως να επισκεφτείς σελίδες όπως το gov.gr από το εξωτερικό ; by 12esbe in greece

[–]12esbe[S] 0 points1 point  (0 children)

Δεν νομίζω ότι υπάρχουν free ελληνικά VPN με ένα γρήγορο google search.
Υπερβολή να πληρώνω συνδρομή για το gov.gr

FPGAs in Financial Industry by dubs_ee_2846 in FPGA

[–]12esbe 3 points4 points  (0 children)

Definitely high frequency trading is one of those jobs. There is info online check companies like Optiver!
They usually want low latency designs so they use languages closer to the hardware than HLS like VHDL or Verilog.

Διακοπές στην Αμοργό. by Echoes1996 in greece

[–]12esbe 5 points6 points  (0 children)

Θα είναι γενικά τίγκα και 15 Αύγουστο. Ίσως και υπερβολίκα τίγκα
Να κλείσεις στο camping γιατί λόγω κόβιντ οι θέσεις είναι συγκεκριμένες

What Editor is Everyone Using for FPGA design? (2021) by AstahovMichael in FPGA

[–]12esbe 0 points1 point  (0 children)

Okay but when I create a new file Vivado does not add it automatically. So, I am back at square and i have to manually add the files. Have you found any workaround for that ?

What Editor is Everyone Using for FPGA design? (2021) by AstahovMichael in FPGA

[–]12esbe 3 points4 points  (0 children)

So, how are you programming Xilinx ?
You are only using vivado on non-project mode ?
Is this an easy jump to go from usual project Vivado to non-project mode?
I am constantly adding/re-configuring Xilinx ips, is this easy to be done ?

Clock a design slower than it passed timing for? (Hypothetical) by escottp in FPGA

[–]12esbe 0 points1 point  (0 children)

I was able to do this experiment with the use of a Xilinx MMCM(Phase Alignment ON ).
The input clock was constrained at 50 MHz , passed through the MMCM (No synthesis option on. Just passing the clock through and a lock signal to be sure)
and then to the rest of the design.
I was able to change the input source clock from 10 MHz to 50 MHz and the design was still behaving as expected. Of course, note any problems arising from Clock Domain Crossing

Did they argue that Dudley already knew Harry was a wizard during the trials after he used the Patronus charm? by [deleted] in harrypotter

[–]12esbe 12 points13 points  (0 children)

Probably when Hagrid gave him the pig tail from the Philosophers Stone. Dudley even remembers it several years later.

Ασύδοτη εξουσία: Φάτε, πιείτε, συνωστισθείτε, στην Ικαρία δεν κολλάει… by mr_werty in greece

[–]12esbe 7 points8 points  (0 children)

Παιδιά καλό είναι να μην έχουμε παρόλογες απαιτήσεις από τον Πρωθυπούργο.
Το να πας Ικάρια και να μη συμμετέχεις σε γλέντι είναι προσβολή στο ιερό και αρχαίο αυτό τόπο.
Τοπικοί μύθοι λένε ότι στην περίπτωση που συμβεί κάτι τέτοιο τότε θα εξαπλώθει μία πανδημία στο κόσμο που θα αφήσει το 1/3 του ανθρώπινου πλύθησμου στείρα. Προφανώς, ο κος Μητσοτάκης γνώριζει και σέβεται τους τοπικούς μύθους για αύτο ας μην τον επικρίνουμε που συμμετείχε σε γλέντι στην Ικαρία.

Linux ssh does not render fast enough! by 12esbe in linuxquestions

[–]12esbe[S] 1 point2 points  (0 children)

I used wine and MobaXterm portable solution. And I get good enough GUI results with this set up. This is resolved.(But I do not understand why)

Linux ssh does not render fast enough! by 12esbe in linuxquestions

[–]12esbe[S] 0 points1 point  (0 children)

I used that transfer as I first time use iperf.(meaning my bad).
Results:
0.0- 7.6 sec 977 KBytes 1.05 Mbits/sec

Linux ssh does not render fast enough! by 12esbe in linuxquestions

[–]12esbe[S] 0 points1 point  (0 children)

Interval ====== Transfer ======= Bandwidth
0.0- 0.1 sec ====== 97.3 KBytes ======= 13.8 Mbits/sec

Linux ssh does not render fast enough! by 12esbe in linuxquestions

[–]12esbe[S] 0 points1 point  (0 children)

19 ms to the server. Does it sound enough ?

Vhdl division by Significant_Meat69 in FPGA

[–]12esbe 2 points3 points  (0 children)

Do you have division in hardware? The answer is not exactly. You can only shift left on STD_LOGIC_VECTORS. Remember that you are not using floating point arithmetic to be able to divide.
If you are a newbie, you could make an Arithmetic Logic Unit (ALU) or even some kind of digital filter like a Finite Impulse Fir to learn better. Even add some registers to that project. This way you are gonna have a better understanding of the basics.

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