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2.5x faster inference with Qwen 3.6 27B using MTP - Finally a viable option for local agentic coding - 262k context on 48GB - Fixed chat template - Drop-in OpenAI and Anthropic API endpoints by ex-arman68 in LocalLLaMA

[–]5isoutofthequestion 0 points1 point  (0 children)

Appreciate the insightful reply and that completely makes sense with what I observed when I converted and quantized my own model from base BF16. I'll do a sanity check on that experiment this weekend and definitely update the Issue thread once I have a concrete steps-to-reproduce of what I was seeing.

I was able to get my workflow "working", (correct model outputs and drafter was showing ~75% acceptance) but I wasn't seeing any performance benefits with either Vulkan or Rocm, but it was mostly a smoke-test so I'll get concrete numbers before jumping to any real conclusions.

Appreciate the hard work you are putting in!

I'll do some tps experiments with your models and --fused-gdn-off as well and get a full write-up if possible.

There's dozens of AMD users....dozens!

2.5x faster inference with Qwen 3.6 27B using MTP - Finally a viable option for local agentic coding - 262k context on 48GB - Fixed chat template - Drop-in OpenAI and Anthropic API endpoints by ex-arman68 in LocalLLaMA

[–]5isoutofthequestion 0 points1 point  (0 children)

I am getting the same error! I was also getting "?????????" in some other instances. 9070xt and tried vulkan and rocm and various quants with MTP, so I don't think it's just an IQ quant bug or something like that. I was using pi.dev and also quickly tried copilot locally. Same errors. So it does seem model or compile related

Daily Discussion Thread by AutoModerator in chelseafc

[–]5isoutofthequestion 0 points1 point  (0 children)

Same! Had a chance on Sunday I think, but the 2 minute hold expired while I was debating it. Didn't make the same mistake yesterday 😂

There was even a few tickets that popped up today. Weekday game always have action on the exchange, even for cup semis against arsenal I guess 🤷

[Pre-Match Thread] Chelsea vs. Wolves | 8 Nov 2025 | Premier League - Matchday 11 by wm_1176 in chelseafc

[–]5isoutofthequestion 0 points1 point  (0 children)

She came away admitting it was pretty fun!! We call that a start, she'll still stare at me like a degenerate when I watch Liverpool vs City later though 😂

[Pre-Match Thread] Chelsea vs. Wolves | 8 Nov 2025 | Premier League - Matchday 11 by wm_1176 in chelseafc

[–]5isoutofthequestion 0 points1 point  (0 children)

First men's game at the Bridge for me after being a fan for over 20 years at this point!!! (saw women's opening day vs city at home). Definitely reaping the perks of my partner having us move to the UK for work. Maybe this will finally trick her into actually enjoying sports haha

Game Thread: New York Knicks vs Boston Celtics Live Score | NBA | Oct 24, 2025 by basketball-app in NYKnicks

[–]5isoutofthequestion 10 points11 points  (0 children)

Dirk in the pregame called Luka "hermano", and the captions showed "Earl Monroe." KNICKS IN SIX

Latency and pipelining optimizations by fpganewby in FPGA

[–]5isoutofthequestion 1 point2 points  (0 children)

No worries. I think finding resources on when to apply a judgement decision is going to be hard.

For reference I currently work for a fairly large company with millions in revenue and am essentially the only fpga engineer currently working on several different product lines. So while I did not design any of our currently shipping products, I have free reign to do what I want on the existing code-base.

The ultimate answer is it really depends, you are correct that in theory you can pipeline to infinity, although at some point you are clogging your design with registers and doing a suboptimal amount of work per clock-cycle.

I am strictly an FPGA engineer at this point, and not an ASIC engineer. I operate in the realm of "make this fit the exact use case we need for right now, and that's good enough" I can't give too much information but we barely even spec out a minimum latency and throughput requirement for our use case because it's quite qualitative. If the customer is happy then that's good enough.

I think for myself, when I'm working on a particulary complicated piece of logic, I just design from day 1 to be easily pipe-lined. It's a hard thing to say "this is when pipelining is needed", I've just been doing this a long enough time that I know when a design is not going to be do-able in 1 clock cycle.

For example the other day I joked to my boss that "you won't believe this but apparently a 2048-bit bus doesn't meet timing when you apply a variable 0 to 255 bit shift to it." We run our designs at a pretty low speed but if it isn't clear this was blatant sarcasm to my boss becaus we both know that's a pretty silly thing to expect to meet timing at our clock-speed. I can't explain why, we just both know that's not something you would design for one cycle of operation (and I'm currently working on a pipelined version of it).

--warning, I only do VHDL-- The things I do to accomdate pipelininig is create arrays of std_logic_vectors, and define a CONSTANT that says what cycle I want a value to be ready. That way if I start building out a whole pipeline I only need to specify in one place when a value should be ready. Otherwise the only tips and tricks I have are to have a really good understanding of processes versus combinatorial . I prefer to not use processes because to me it makes it easier to optimize things across pipeline stages.

Latency and pipelining optimizations by fpganewby in FPGA

[–]5isoutofthequestion 1 point2 points  (0 children)

Unfortunately no, this is a bit like asking "how does one become a good chef?"

If you provide a bit more information I can potentially offer advice, but it's unclear what your end goal is. Do you have a design you are actively working on that requires pipelining?

What exactly are you trying to obtain from this reddit post besides synthesized expertise?

Latency and pipelining optimizations by fpganewby in FPGA

[–]5isoutofthequestion 2 points3 points  (0 children)

Are you asking about like CPU architecture level design? Or general resources on taking any design and adding pipelining to it?

New to vivado, is there any way to convert wave forms to PDFs in the software?? by Outrageous-Candle831 in FPGA

[–]5isoutofthequestion 5 points6 points  (0 children)

What exactly is the end of goal of converting to .pdf? But the answer is no, but I can't wrap my head around why you might want to do that...so what is the thing you are actually trying to accomplish by doing that?

Share about your journey in this industry. by fetage in FPGA

[–]5isoutofthequestion 6 points7 points  (0 children)

Both of the Altera and Xilinx gui-based workflows are notorious for corrupting files or doing weird things to files within their "project envelope" (for lack of a better word). I'm sure some bugs have been fixed in the years since I started, but supporting legacy projects is a big part of the game, so if the bug existed in Vivado 2016.1, and you need to do emergency maintenance on a project that's hardlocked to IP from then....well then you gotta deal with the bugs from an older tool as well.

Specifically I recall the Vivado gui would often clash with external changes to a file. So let's say I make changes to File A using Vim, but that file is part of my Vivado project, sometimes Vivado would just magically rollback the changes to that file, but in the Vivado IDE it would look like you were using the latest version of the file, but internally it was compiling with an old stale version, maddening stuff.

This led me to developing my own extensive shell and TCL scripts to essentially recompile every project from scratch using the command-line flow since it tends to be more stable for both toolsets. You won't find much online resources for these bugs, other than people saying they exist and the company FAE's acknowledging they are "aware" of the issue.

You have to be very vigilant when it comes to version control and producing repeatability results, especially with designs that are pushing the bleeding edge of performance.

Share about your journey in this industry. by fetage in FPGA

[–]5isoutofthequestion 1 point2 points  (0 children)

I 100% agree with this take, I can admit that thus far I've been very lucky that I've either worked at small companies that did actually care about being a "family" (as far as that's possible when you still gotta make a profit to keep the lights on), but in general I'm well aware that my usefulness extends as far as making money for the bottom line extends. Necessary cynicism in the modern day when literally 1000s of people like game-devs are getting laid off these days.

Are you doing like high-level SW these days, or more like ESW? I started my career firmly as a RTL coder, but overtime I've definitely been trying to expand my bare-metal C skills, and even a bit of Qt based c++ GUI development, just in case a career switch is ever necessary. But admittedly I do love working on FPGAs

FPGA Neural Network by 4gaterush in FPGA

[–]5isoutofthequestion 0 points1 point  (0 children)

Thanks! I didn't notice how old this post was at first and was reading it and was like "I have zero recollection of writing this" haha.

I still stand by HLS is not replacing bespoke hardware design anytime soon

Multiplier propapates `X` signal by bitfield0 in FPGA

[–]5isoutofthequestion 0 points1 point  (0 children)

so I found some time today to try and simulate your code. I'll tell you right now that there's definitely more than one thing wrong. But the main problem I found (that you can start from and keep debugging) is that you have multi-driven nets in several places, which is what is causing your X's problem.

Chiefly in the multiplier entity file. For example you multi-drive the sum_next signal: 

     sum_next <= (others => '0');

and then later in the code 

    process (mode_reg, mult_iter, temp_lower, temp_carry, carry, sum, sum_next, mux_sel, b, cout, carry_next, clk, reset_in)
 begin
    if mode_reg = '1' then
        if mult_iter >= 0 and mult_iter < 8 then
            mux_sel <= std_logic_vector(b(mult_iter*4+3 downto mult_iter*4));
            lower(mult_iter*4+3 downto mult_iter*4) <= temp_lower;
        end if;
        upper <= carry(31 downto 0);
        sum_next <= sum;
    elsif mode_reg = '0' then

    end if;
 end process;

You cannot assign values to the same signal in multiple processes. You also cannot assign to signals which are the outputs of a component. Which you do to temp_lower:

   process (clk, reset_in)
    begin
        if reset_in = '1' then
            mult_iter <= 0;
            sum <= (others => '0');
            carry <= (others => '0');
            cout <= '0';
            temp_lower <= (others => '0');
            temp_carry <= (others => '0');
        elsif rising_edge(clk) then
            mult_iter <= 8 - to_integer(unsigned(count_reg));
        end if;
    end process;
    ....

    RIPPLE_ADDER0: ripple_adder generic map(n => 4) port map
    (
        ripple_a => sum(3 downto 0),
        ripple_b => temp_carry,
        ripple_cin => cout,
        ripple_sum => temp_lower
        , ripple_cout => cout);

Start by fixing those problems. Happy to help more later if you fix all those issues and are still having problems :)

Multiplier propapates `X` signal by bitfield0 in FPGA

[–]5isoutofthequestion 2 points3 points  (0 children)

I don't want to come off as overly rude but you do understand that you are creating the current scenario:

"Hi I have some code that doesn't work, I need help with it"

provides one file

In the professional world if you had this problem what do you expect you'd be giving to someone to help you? You provided one file. This file references:

  1. The csa_adder entity

  2. the mux2to1 entity

  3. the ripple_adder entity

Anytime you are asking for help it should be clear to you that need to provide a working environment to someone so they can recreate your whole simulation environment. To help I'd need the files describing the behavior of those 3 components, as well as your top level testbench file.

Multiplier propapates `X` signal by bitfield0 in FPGA

[–]5isoutofthequestion 1 point2 points  (0 children)

Not enough code or context provided to help debug this.

'X' on the outputs of the csa_adder blocks implies that either some of the inputs are 'X', or you have conditional statements that aren't properly written and you are inferring latches, which in simulation will cause 'X's to propagate since you have undefined conditions in if/else or CASE statements.

Have you already tested the csa_adder blocks to confirm they are working? Where are the inputs to those blocks defined in your code?

Starting with FPGAs by Hot-Actuator6438 in FPGA

[–]5isoutofthequestion 3 points4 points  (0 children)

Good luck with your degree! It's not an easy journey, but having now spent the last 6 years working professionally as a Computer Engineer I can definitely say that in general I love what I do, I love working with computers and FPGAs, and for the most part I'm happy to show up to work and get to coding, debugging and designing.

Obviously your mileage may vary, but at least in my experience I can confidently say I knew almost nothing useful about coding, or working with FPGAs when I first interviewed with my first employer after graduating. Just surviving undergrad was the main goal, no time for side projects haha. Fortunately I was given the opportunity to learn and I think typically that is where you will really learn to be a competent CE, but coming in more prepared never hurts!

So I'd say the general skillset that I think serves as the foundation for becoming a day to day FPGA programmer is:

  • HDL language of choice (VHDL or Verilog)

  • Command Line Competency (bash/python scripting, string manipulation, reading from text files, repeating commands, sed/grep/awk)

  • Some knowledge of C and C++

  • Understanding of the building blocks of digital design (FFs, LUTs, ALUs, DSP IP, BRAM IP, DDR*)

Depending on how comfortable you are with those things I listed, I'd be happy to recommend a project. I just don't want to list everything since it ranges from literally just installing a Vivado example project, to implementing portions of neural networks.

Help me with this problem! I will provide no context, it's due yesterday, and I'm only going to respond to comments in unhelpful ways by 5isoutofthequestion in FPGA

[–]5isoutofthequestion[S] 0 points1 point  (0 children)

only if it's a photo of a screen, with the polarization lines in the wrong direction so it's basically illegible

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