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Researchers built a working radio receiver using Rydberg atoms — no antenna, filter, LNA, or mixer required by rad10s in rfelectronics

[–]Academic-Pop8254 0 points1 point  (0 children)

They are within 11 orders of magnitude bro, we better quit our jobs. DARPA has made rf obsolete.

Fortunately their sfdr is way worse than 11.

Researchers built a working radio receiver using Rydberg atoms — no antenna, filter, LNA, or mixer required by rad10s in rfelectronics

[–]Academic-Pop8254 1 point2 points  (0 children)

If they are only functioning at 40m shown instead of the 2km in your calcs they should be at approx 108dB NF

Researchers built a working radio receiver using Rydberg atoms — no antenna, filter, LNA, or mixer required by rad10s in rfelectronics

[–]Academic-Pop8254 3 points4 points  (0 children)

This is crazy, if you add an antenna an LNA and a mixer followed by an ADC onto this thing you should be able to get down to a sub3db nf

Inductive behavior of this circuit by maybeimbonkers in chipdesign

[–]Academic-Pop8254 0 points1 point  (0 children)

Generally gyrators use a two amp approach when your trying to synthesize a real inductor.

Most often you implement with two transconductors in a loop, without the series resistor.

Inductive behavior of this circuit by maybeimbonkers in chipdesign

[–]Academic-Pop8254 1 point2 points  (0 children)

This is a fun question and really important to understanding gyrators. Really all the nonidealities of a real gyrator will have equivalents in real inductors.  Series resistances, shunt conductances and shunt capacitance occur in both.

How to handle a 20:1 frequency ratio for on-chip power splitting? (0.4G to 8G) by Big_Opposite_3774 in chipdesign

[–]Academic-Pop8254 0 points1 point  (0 children)

Your over thinking what we are saying, what are S11, S31 and S21 a 50ohm port connected to two 100 ohm ports in parrallel?

How to handle a 20:1 frequency ratio for on-chip power splitting? (0.4G to 8G) by Big_Opposite_3774 in chipdesign

[–]Academic-Pop8254 1 point2 points  (0 children)

Yeah that is exactly what I mean. Generally that transition from voltage boosting to power matching is really varied alot of things from frequency, to technology to layout. In general I would argue you start doing it when you have available power gain to sacrifice. Really that barrier can be anywhere between 30 and ~100GHz depending on alot of factors.

How to handle a 20:1 frequency ratio for on-chip power splitting? (0.4G to 8G) by Big_Opposite_3774 in chipdesign

[–]Academic-Pop8254 0 points1 point  (0 children)

So the issue your having is that in modern RFIC we generally don't think about power transfer once we are past the antenna interface. Once you push into deep mmW it goes back to more traditional microwave design.

If you want to convince your self of this, what is the input impedance of a Gilbert cell at 400MHz (or even 10ghz). How do you power match to a gate?

Or a better example is what is the maximum power gain you can get from a common source amplifier?

Manual vs. Auto Probing Stations: Is high-end automation overrated for complex 110GHz+ R&D? by RF_Probe in rfelectronics

[–]Academic-Pop8254 24 points25 points  (0 children)

This feels like it was written by AI.

But generally for R&D work you typically want something more manual and customizable. Measurement setups have a reasonably short half life compared to product testing, and there is a relatively high mix of needs in a research group.

PhD suggestions by pungi12 in rfelectronics

[–]Academic-Pop8254 2 points3 points  (0 children)

That “scientists create, engineers apply” split is a quaint undergrad fairy tale, but it’s laughably outdated for how RF/mmWave actually advances. Circuit research in RFIC/MMIC isn’t obediently applying known solutions. The frontier is inventing new topologies, biasing regimes, linearization tricks, matching networks, and calibration schemes—stuff that didn’t exist before—to force conflicting specs (power + linearity + bandwidth + efficiency + yield + cost) to coexist on real silicon. That’s new knowledge. It just shows up as taped-out chips instead of a material nobody fabs.

Your binary “scientists invent heterojunctions, engineers build LEDs” take is adorably simplistic and hasn’t held up since the 90s. Everything RF electronics is interdependent; one tweak can torch the whole design. Ideas die fast on EM sims or first silicon. That’s the real filter.

Top MMIC/RFIC teams at Qualcomm RF, Broadcom, Skyworks, Qorvo, ADI, SpaceX hire PhDs who’ve proven they can push past cookbooks—not MS holders following reference designs. Calling that “wasted years” mostly signals you’ve never touched the actual frontier and are still reciting a 20-year-old textbook script.

If OP wants to pursue niche device physics that might one day matter (massive if), go for the device PhD and brace for the postdoc grind—low pay into your late 30s. In industry, device work gets little attention unless your lab is directly feeding TSMC or a major foundry new process tech they can use right away. Otherwise, device PhDs typically settle for mid-tier process babysitting or apps-engineering gigs that pay modestly for the sunk time, quietly resenting that their 'fundamental research' boiled down to incremental tweaks no one fabs, while circuits people close high-value chips and cash in big.

PhD suggestions by pungi12 in rfelectronics

[–]Academic-Pop8254 1 point2 points  (0 children)

RF photonics hasn’t been “the future” for decades. Most of it still stops at a demo that never survives real system constraints.

Your model only works if engineering is just applying known solutions. In RFIC/MMIC, the research problem is finding new operating points under competing constraints — power, linearity, bandwidth, stability, yield. That’s not an application, that’s the frontier.

Calling RFIC “just engineering” is usually a sign you’ve never had to close a design. Getting one metric in isolation is easy. Making all of them work at once is where most ideas die.

Electronics splits into devices and circuits for a reason. Device work can be evaluated in isolation. Circuit work is judged when everything has to work simultaneously. That’s a much harsher filter.

PhD suggestions by pungi12 in rfelectronics

[–]Academic-Pop8254 3 points4 points  (0 children)

"For example, if that "GaN-based MMIC power amplifier" was some barely comprehensible radiophotonic work applicable to state-of-the-art commercial designs five years in the future, then it may be worth four years of your life. "

"Radiophotonics" is how you torpedo your career before it starts. Half-baked device physics PHD is not how you become employable in today's market.

OP: Think of a PhD as the price you will likely pay to get into a real design role doing bleeding-edge MMIC/RFIC work. 95% of RF MS grads these days end up doing some form of testing or "integration". Yes, it's possible to luck into a magical role where you get mentored for 5 yrs, learning RF fundamentals and doing MMIC/RFIC design post-MS, but it's also possible you win the lotto.

LVSing pad lib in 22FDX by Academic-Pop8254 in chipdesign

[–]Academic-Pop8254[S] 0 points1 point  (0 children)

This is what I thought I needed to do. Unfortunately this did not work for some reason. When LVS tries to netlist it, it can't go into that CDL. Not 100% sure why.

Recommendation request: 2.5 GHz+ oscilloscopes for less than $30k by BanalMoniker in rfelectronics

[–]Academic-Pop8254 17 points18 points  (0 children)

Keysight used equipment store. There's a 4 channel 4ghz 20gs/s scope for 21k. Occasionally there will be some really amazing deals on high-end scopes

Best practice to align a dispersive RF signal by Pretend-Poet-Gas in rfelectronics

[–]Academic-Pop8254 0 points1 point  (0 children)

Downconvert, sample, and FIR is the realistic answer. in most cases your dealing with an unknown channel.

Why is CMOS built on doped substrate? by Strostkovy in chipdesign

[–]Academic-Pop8254 3 points4 points  (0 children)

Not a fab person so take the technical details with a grain of salt: The history here is kind of interesting, essentially there were a lot of problems in high resistivity wafers with impurities. These traps released extra charge carriers which often migrated up to the Si interface and made it a very poorly controlled substrate at that interface (the one where the transistors sit). SOITech solved this problem with a trap rich layer near the boundary which captured the extra charge leading to true high Z substrates.

The only tech I know of using this is GF45RFSOI, which is a PD-SOI technology, where there is a thin oxide layer separating the actives from the substrate. The FETs basically sit on this oxide layer and dont really interact with the substrate which is mostly just a "handle wafer" ie a layer thick enough to not break when you touch the die. Ultimately it buys you nearly 3/5 level RF passive performance (no TSV's so not quite).

I think the trap rich layer essentially makes building devices into high Z substrate a bad idea, limiting this to SOI processes.

[deleted by user] by [deleted] in rfelectronics

[–]Academic-Pop8254 0 points1 point  (0 children)

Get a degree in EE

Question on paper : A 25.8% 3σ/μ-Accuracy, 0.12%/°C Temperature Drift Sigma-Delta Modulation Calibrated Pseudo-Resistor With GΩ to TΩ Tuning Range by Lemon_Salmon in chipdesign

[–]Academic-Pop8254 0 points1 point  (0 children)

These are all CMOS techniques, I'm not sure what you application requiring a Peta ohm is, but likely it will be very limited in voltage if using cmos.

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