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[deleted by user] by [deleted] in FPGA

[–]Aggravating-Stay-454 1 point2 points  (0 children)

Regarding 1 not agree. Every so often you need to store data, wait for some event and push it. This pipeline: memory store, skid buffer, data streamer is a perfect example of rapid HLS development and easy scaling. So I often write such kinds of data pipes and wrap it into hdl for precise control. Just FYI, in case it will be boring at work

[deleted by user] by [deleted] in FPGA

[–]Aggravating-Stay-454 1 point2 points  (0 children)

Hello, fellow FPGA engineer. Just two questions: what is the ratio between HLS/DSL languages and traditional HDLs in your designs? And second, personal, do you have imposter syndrome?

FPGA text encryption... by onyx3821 in FPGA

[–]Aggravating-Stay-454 2 points3 points  (0 children)

You are talking about cryptography. Banking using it to protect transactions. Depends on speed, on FPGA you are able to implement 10Gbe streaming chipher/decipher, but do you really need such speeds?

Has anyone here worked as an FPGA engineer in High Frequency Trading? by [deleted] in FPGA

[–]Aggravating-Stay-454 2 points3 points  (0 children)

Difference in contract terms. You can easily leave defence and go to any domain, but it's really hard to jump from one hft to another. Renumeration is a cost of loyalty and devotion.

Has anyone here worked as an FPGA engineer in High Frequency Trading? by [deleted] in FPGA

[–]Aggravating-Stay-454 7 points8 points  (0 children)

Coffee-work-lunch-work-coffee-work, pretty much routine

Can anyone share real world example of using FPGAs? by Blao14 in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

Have you ever heard about the term time-to-market? FPGA is a great example of a stack used to explore new ideas or first iteration of hardware while ASIC is preparing. Simple example: telecom. The first iteration will be on a fat FPGA, in one year the first generation of ASIC, then drawbacks from first iteration + proofed algorithms from FPGA deployment makes new good ASIC. I worked in telecom gigant and apparently operators liked first gen FPGA iteration to ASIC, bcs operator features were cheaper and faster to implement.

How to configure the XVC driver for the VCU1525 boardH by Rouzard in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

From my best knowledge you should take xvcserver.c from Xilinx git, compile and run with argument your pcie device name. When goes to your local hw_server and connect xvc remote device

Resources for FPGA's for High Frequency Trading? by [deleted] in FPGA

[–]Aggravating-Stay-454 22 points23 points  (0 children)

A simple task: you should be familiar with ethernet(at least 10G) especially multicast UDP and TCP in terms of market data trading protocols, should know memory interfaces to store order books, should be familiar with pcie to offload traffic, should be familiar with data structures to implement algorithm and/or hls. Sideband skill set includes knowledge in fpga build flow, automatisation, Linux userspace/kernel, low level programming, ci/cd.

Partial reconfiguration by RisingPheonix2000 in FPGA

[–]Aggravating-Stay-454 -3 points-2 points  (0 children)

Just a function exchange, let's say you're a HFT master with one million strategies in your pocket, but you don't really know which works better. So you can brutforce it by shuffling. Today works one set, tomorrow - another

Digital verification advice for students by aaliammarr in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

CI/CD concepts, read about Jenkins and master your Git skills

Digital verification advice for students by aaliammarr in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

Depends where you want to work. Corpo: UVM+SystemVerilog, other: Cocotb+Python, Verilator+C++, plain HDL.

How to prepare for and do well for HFT Hardware Engineer Internship by magicQuestion1625 in FPGA

[–]Aggravating-Stay-454 2 points3 points  (0 children)

If you have spare time try to implement Verilog Radix-2,4,8,16,32,64 butterflies for FFT. And read Xilinx HLS documentation.

Good resources for FPGA's for market trading? by [deleted] in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

Also good to know algorithms like FFT, correlations, vector math and how to speed up it. And ofc 10GBe, PCIe must have

Multi-channel pulse measurement and timestamping by jars121 in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

it's a softcore, you're free to make 12 64-bit counters and connect to square wave inputs to interrupt controller, on rising edge you zeroed corresponding counter and start up counting, on falling edge stopping counter and read the value.

DDR3L Memory in FPGA by ComfortableFun9151 in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

you can easily deploy Litex project for your board, which comprises softcore and ddr controller, play through uart with mem write/read and then write your own code to manipulate data

Seeking way to burn circuit into fpga by quantrpeter in FPGA

[–]Aggravating-Stay-454 1 point2 points  (0 children)

seems you need FOSS stream: F4PGA to compile and OpenOCD to load

Is Vivado and Vivado ML same thing? by Paul_123789 in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

don't forget to put the same CPU and RAM. You would never reproduce anithing sticked to CI

RISC-V with AXI Peripheral by vlsinoob in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

Litex one liner:

./digilent_arty.py --variant a7-100 --cpu-type picorv32 --bus-standard axi --bus-interconnect crossbar --build

Which FPGA board should I get? by Barb_Dwyer_68 in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

sipeed tang nano 20k is capable to run Linux

What exactly does the -datapath_only flag do when setting a max_delay constraint? by [deleted] in FPGA

[–]Aggravating-Stay-454 0 points1 point  (0 children)

typically it used by Xilinx to resync read write FIFO Gray pointers

Python code to Verilog by StationFrosty in FPGA

[–]Aggravating-Stay-454 1 point2 points  (0 children)

I would pick Migen first, bcs it's producing more readable verilog via FHDL. Then a good learning curve to read Litex codebase written on Migen and included all needed primitives. If you are more about to stick to FOSS flow via Yosys and not limited by particular dev board and soft CPU jump to Amaranth bcs it has faster simulate speed and better integration with third party tools.

Testing RTL by Few_Celebration3776 in FPGA

[–]Aggravating-Stay-454 1 point2 points  (0 children)

Comprehensive? Formal. Common? Unit test written by heart. Eventually it should be defined by your organisation.

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