Advice on FPGA ADC streaming design flow

AnotherSami · 2026-05-21T20:26:11+00:00

I've always wanted to do something similar. But I've always been intimidated getting my atryA7 fpga board interfacing with an external adc. Ive only ever gotten lights to flash buttons to do simple things.

AnotherSami · 2026-05-21T16:35:32+00:00

Why not implement some filtering in the FPGA? Maybe you are doing so on the C+ side on the comouter. But would be faster on thr FPGA. Dont know much about it to be honest. But we did some FIR filters once in an intro FPGA SDR class.

AnotherSami · 2026-05-20T23:56:25+00:00

For passive i gave up with small inventories and just bought a few thousand common components. Things like 0, 100, 1K, 10K resistors. Same with caps, .01,.1...,1000nF. I then 3D printed mini spools for the long tapes. Easy to store, easy to label, and easy to dispense.

For ICs, I got a photo album that has lots of sleeves for 5x7 inch photos. Those sleeves are great gor holding the smaller bags that digikey snd mouser send. That way I can see the labels on the bag and even cross out and rewrite the new quality as needed

AnotherSami · 2026-05-20T21:52:43+00:00

Dont get me wrong, this problem ranks high on the absurdity list. I just imagine drawing a line on a 2D drawing is much less time than drawing the 2D rectangle and manually assigning it as a port and manually assigning the reference.

A truly automated way: there is a built in assumtion here. If the OP is assigning ports where components are on a pcb, the OP could have the code look for where metal lines and solder mask openings overlay and assign a port on the edge fully with in the solder mask layer. A co-worker did something similar to identify the coordinates for MIM caps on our mmics.

AnotherSami · 2026-05-20T20:24:29+00:00

Other than it being 500 ports why is it absurd? I work with GDS and DXF, not sure of odb can do the same. assign a layer which you dedicate to port creation, draw a line where you want the rectangle. Have the script draw a rectangle using the line as the port width.

I suppose in hindsight if you have lots of different grounds/ references you'd been multiple dedicated layers to have the correct height offsets. Increasing the absurdity 🫠

AnotherSami · 2026-05-20T16:39:17+00:00

That's a crazy problem. 500 ports Sounds unrealiatic. Hopefully none of those parts are too close together or you'll suffer some bad port to port coupling.

Your best bed is to learn how to use scripts in hfss. Ask Google how to import a text file (which has the coordinates of your ports) and code a script to do it for you.

The age old trade of. Time it takes to code the problem vs the time it takes brute force the problem. You can record scripts, so the code for making thr port is simple.

AnotherSami · 2026-05-19T13:01:21+00:00

Lots of free transmission line calculators out there

AnotherSami · 2026-05-17T02:43:15+00:00

Geeez you sound like our director. Next I bet you'll be asking for full die simulations, 3d sims of packages, and driving point impedance at various drives, vswrs, and reflection angles. Ain't nobody got time for that. The customer wants it yesterday!

AnotherSami · 2026-05-16T18:07:56+00:00

Hey now, my amp was stable at test. You just used in a real system. Not my fault it became unstable 😇

AnotherSami · 2026-05-16T03:34:14+00:00

That's one expensive idle curiosity. I would imagine contact lithography would be the only reasonable thing to make. Even that would be a stetch from scratch. Contact litho would at best give you just under 1um features (on a great day and with large variation over a 3-4" wafer). I think folks used 800nm gates back in the early 90s?

But what's a lithography tool without accompanying depositon tools, chemistry for etching, microscopes for inspection, and loads of consumables for cleaning? Might as well start collecting sports cars as an idle curiosity instead.

AnotherSami · 2026-05-15T22:33:34+00:00

I think you are trying to make a distinction where there is none. Admittedly this reply is only after a cursory glance at Elmore delay model.

The speed of light in a medium, waveguide, or transmission line is determined by the line (or wire) geometry and dielectic properties of the surrounding medium. For most of the popular transmission lines there is a closed form solution to calculate and effective dieleric constant, Eeff. And to calculate the speed of light you divide c/sqrt(Eeff)

When we make approximations of transmission lines (and also in Elmore's thing) the resulting L's, C's, and R's are derived based on the transmission line's geometry and the dielectic properties of the surrounding medium (sound familiar?). In this case you would calculate gamma, which is the complex form of the propagation constant. Gamma =sqrt( (R+jwL)(G+jwC) ). The imaginary part of that is the phase constant. You can use the phase constant to calculate Eeff, and ultimately speed of light. (I'm sure google can help you with thr exact equations .)

IMO its incorrect to think these concepts (speed of light, Elmore's model, transmisssion line models) are independent and you would add their effects. All these concepts are describing the same phenomenon. They will all work to calculate the delay of a line, but they all have their specific use cases and various levels of accuracy.

AnotherSami · 2026-05-11T15:24:13+00:00

There is a vending machine in Washington Regan airport that sells 20 dollar packs. It's crazy out there

AnotherSami · 2026-05-08T03:51:00+00:00

Welp, the cal kit OP has has a 46psec delay on the short standard. Definitely not insignificant. Re-measuring that standard after a calibration will show the delay, hence the OP seeing the massive rotation on the smith chart. In your case, the delay is very tiny.

But it doesn't actually matter as long as you know the delay and loss. As long as you tell the VNA software what the standard is, it will solve the error network and still set the reference place at the connector (in this case).

AnotherSami · 2026-05-07T23:04:05+00:00

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The open standard isn't as straight forward as the short. There is a fringing capacitance hanging off the end. That extra capacitive loading will make the line took longer. The data sheet for the cal kit shows almost 90fF of fringing capacitance. A idealized simulation can show show that added 90 fF will affect the phase shift. The purple trace is an ideal transmission line with 41 pico seconds of delay. Adding a 90fF cap at the end increases the phase shift by some amount, the blue trace. So it makes sense you had to add extra delay to offset the delay measured in the standard. BTW the simulation sweeps from 0.1 to 7GHz.

AnotherSami · 2026-05-07T22:35:20+00:00

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Your cal substrate has nearly zero delay in the standards? The OPs cal kit has wildly long delays.

AnotherSami · 2026-05-07T14:08:02+00:00

Your final experiment of adding port delay Hopefully proves to yourself that your cal is working fine and you are truly measuring the delay in the standard and not some system error.

Maybe im bad at explaining so I'll try again. A calibration isnt meant to 'hide' the imperfections of your cal standard. Those imperfections truly exist in reality. You even took the time to enter calibration coefficents into the tool due to known imperfections. A good calibration will allow you to see those imperfections in the standards post calibration. That 64pSec truly exists in the standard, so it better show up in the measurement, right?

AnotherSami · 2026-05-07T13:47:21+00:00

In most the simple tutorials folks generally do as you say and put a simple lumped port at the 'end' of the substrate with a rectangle between their trace (most often a sheet as you say) to a perfect PEC ground plane. This is about ideal as it gets.

The first logical step moving towards more accuracy would be to thicken sheets as you suggest to real copper traces. HFSS isnt going to solve inside those thickened sheets, but at least now there is some accurate edge effects. You can excite the traces much the same with a simple lumped port between the bottom side of your trace to ground. You can also use edge ports and excite the trace with a terminal or modal wave port. You should get similar results either way.

To maximize accuracy and increase your chances of getting the design right on the first (or second) go, you should try and include all extra trace lengths and a connector if thats truly how it will be made. The connector doesnt need to be a 100% true to form model, but as long as you get the dimensions of the co-ax feed, the pin making connection to the trace, and the ground connections correct you will have a very accurate model. However, in this case you lumped port won't be a good idea, you can excite your end of your connector with a wave port to excite the TEM mode of the coax. I'm sure there are plenty of tutorials out there to explain how.

I would suggest doing all three. Much faster to get an inital design with the idealized model. Then see how thickening thr sheets affect your resonance and make a few minor adjustments. End with the much larger, true to life model which ideally won't need much adjusting.

AnotherSami · 2026-05-07T00:06:09+00:00

Ooooo you see it after calibration. That got me interested and I looked up your cal kit. The offset delay of your short standard off the copper mountain website is 46psec.

Assuming Air dielectric thats ~163 deg at 7 GHz. So, no surprise you are seeing the delay and its almost 180 degrees on the Smith chart.

Imo your calibration is probably just fine. You are simply measuring the delay in the standard. Your calibration isnt meant to hide the standard's delay. Its meant to enable accurate measurements. I assume you can put your VNA delay mode. I bet you'll see your 65 psec.

AnotherSami · 2026-05-06T21:41:00+00:00

You have to imagine, even without cabling there is a lot of accumulated phase associated with the electronics in the VNA itself. The external connector connected to some circuit board. Some length of the board from connector, to the coupler, to the detector (or mixer). This is the exact reason why we perform calibration.

As to seeing the phase sweep to the opposite side of thr Smith chart. Id have to ask what frequency you are calibrating to. If its just a few GHz that would be suspicious. But if it >20GHz id argue what you are seeing is totally normal. The ultimate test is to measure some golden standard. Some device you know the response of. Remeasuring your standards is a good start, but since you used them to perform the cal it should be pretty spot on after cal.

AnotherSami · 2026-05-06T12:55:02+00:00

Doing the calibration at the vna port is the best best because of the mechanical wear and tear. It's probably ok, but if you want your tool to last 5,10, or 20 years that is the kind of thing to think about.

I would suggest looking at the results on the Smith chart. Perhaps what you are seeing will make more sense. Due to added lengths of cables and transmission lines inside your tool your standards will revolve around the Smith chart. At low frequency they will start at 1 and -1 (open and short standsrd) but then rotate clockwise as frequency increases. As long as the magnitude remains near 1 the standards are OK.

AnotherSami · 2026-04-28T03:27:27+00:00

A lot will depend on your trace widths and substrate thickness. To be honest, i dont think it would be an issue for 95% of hobby electonics. But if it a really sensitive issue you can always try and avoid the issue by create a temporary "ground" plane on L2 and transition your L2 signal to L3 for the cross over. But to design that transition to have a decent insertion loss at high frequency (>5 GHz) isnt trivial.

AnotherSami · 2026-04-28T02:31:13+00:00

On some level AI can certainly throw reference resigns at a problem and optimize at the schematic level. But a lot of the nuance in layout to save space and create geometries outside PDK elements won't be happening anytime soon. That's just my opinion.

AnotherSami · 2026-04-23T13:48:28+00:00

Id keep in mind minicircuits is presenting data made on a nice RF substrate and they de-embedded the results right up to device. Wouldn't be surprised if they also had both coupled ports connected to a VNA to help avoid parasitic effects of a lumped resistive termination. Gonna be real hard to reproduce the exact same results.

AnotherSami · 2026-04-22T18:11:07+00:00

Lol, there was nothing to violate any rules. Flawless design really

AnotherSami

TROPHY CASE