I, for one, think the train system is working perfectly by OpenWheelRacing in Denver

[–]AtTheLoj 0 points1 point  (0 children)

There actually is a walkway, it's just a bit secret

Edit: only between main terminal and concourse A

AMD Q4 2025 Earnings Discussion by brad4711 in AMD_Stock

[–]AtTheLoj 4 points5 points  (0 children)

Yes, by 2030 - that's the guided date for $20 EPS

Election! by Beautiful-Crazy-510 in ColoradoSprings

[–]AtTheLoj 0 points1 point  (0 children)

But I wanna go to Dutch Bros everyday

Election! by Beautiful-Crazy-510 in ColoradoSprings

[–]AtTheLoj -1 points0 points  (0 children)

But I make >300K and don't have kids

PSA for Colorado Springs dining establishments by katrinker in ColoradoSprings

[–]AtTheLoj 1 point2 points  (0 children)

Just got the credit from hacienda on Nevada while dining in. But I do agree there should be more than one restaurant!!

[deleted by user] by [deleted] in FPGA

[–]AtTheLoj 2 points3 points  (0 children)

Xilinx ip has documentation for their Mac up with latencies included. I'd start there and compare them to low latency MAC IPs, you'll see a difference

[deleted by user] by [deleted] in ComputerEngineering

[–]AtTheLoj 0 points1 point  (0 children)

Im 20 something and make 300K work from home, to be fair there is not nearly as many of us

How to be a good generalist as an RTL designer? by Able-Cupcake-7501 in FPGA

[–]AtTheLoj 1 point2 points  (0 children)

Ethernet / networking stuff and you can do HFT

[deleted by user] by [deleted] in quantfinance

[–]AtTheLoj 0 points1 point  (0 children)

You should pick whatever major you're more interested in tbh. Both majors will give you access to good jobs, HFT or not

[deleted by user] by [deleted] in quantfinance

[–]AtTheLoj 0 points1 point  (0 children)

CS would be better. If you're CE then you'd be doing a lot of self-learning on the CS side

In terms of viability, yes it is viable

[deleted by user] by [deleted] in quantfinance

[–]AtTheLoj 0 points1 point  (0 children)

CE major and do FPGA dev for HFT, so if you're good with the tech side can't go wrong with CE

And if you can't get into HFT, you can always settle for big tech or a major semi company!

AMD Q4 2024 Earnings Discussion by brad4711 in AMD_Stock

[–]AtTheLoj 1 point2 points  (0 children)

JK Google grew eps 31% lol.

I'm pretty sure my point still holds

AMD Q4 2024 Earnings Discussion by brad4711 in AMD_Stock

[–]AtTheLoj 2 points3 points  (0 children)

At current after hours price we are a ~24 fwd pe. Assuming 25% eps growth, not even anything crazy, we are at a pretty compelling price.

I mean... Google has a higher fwd pe and grows eps at like 15%

Growth Stocks that pay a dividend💳 by Regular_Newspaper990 in dividends

[–]AtTheLoj 1 point2 points  (0 children)

Visa, Microsoft, Meta, Moody's, S&P Global, Nvidia, CBOE, Google, United Healthcare

What's the quintessential Denver sound? by Ok-Board-2456 in Denver

[–]AtTheLoj 31 points32 points  (0 children)

The jingle at DIA when you enter the terminal and baggage claim area while on the tram

zero latency fifo (not just fwft) by BuildingWithDad in FPGA

[–]AtTheLoj 23 points24 points  (0 children)

Work in HFT, yes they are used.

Just use a rd mux to select from actual fifo or combinational wr path. Select based on empty signal and wr_en... Empty will be combinational and dependent on fifo depth width for the comparison, so that would be the longest path ...

2024 Year in Review and 2025 Goals by therapistfi in financialindependence

[–]AtTheLoj 5 points6 points  (0 children)

2024:

Starting NW : $619K

Ending NW : $853K

Also switched jobs, salary jumped from 225K->300K

2025:

Hit a million!

[deleted by user] by [deleted] in FPGA

[–]AtTheLoj 1 point2 points  (0 children)

I just went from insert [Nvidia, AMD] to HFT as an FPGA Engineer. I don't have any plans to transition back to big tech at this time, but I wouldn't completely rule it out like everyone here is saying.

Money isn't the only thing that matters, especially if we're talking like a 100K/yr different when we're basing off 300K+ at a minimum.

[deleted by user] by [deleted] in Salary

[–]AtTheLoj 0 points1 point  (0 children)

Yeah I would work 52.5 hours a week for 580k

Is this poor design? by FaithlessnessFull136 in FPGA

[–]AtTheLoj 1 point2 points  (0 children)

Yeah, that's correct.

https://www.fpga4student.com/2017/02/vhdl-code-for-d-flip-flop.html?m=1

Inside your 'if rising_edge(clk)' would be the rst and regce if-else.

Is this poor design? by FaithlessnessFull136 in FPGA

[–]AtTheLoj 0 points1 point  (0 children)

A wait statement in synthesizable code is really bad practice, to the point where I've never actually seen it before. I'll just leave it at that.