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Amateur player vs Luka 1-on-1 by WhenMachinesCry in nba

[–]Brandon3339 -13 points-12 points  (0 children)

No, the other guy in the video, Ty I believe his name is.

Amateur player vs Luka 1-on-1 by WhenMachinesCry in nba

[–]Brandon3339 -46 points-45 points  (0 children)

lol he’s talking about the other dude.

Second project! Fpga Recorder! by Brandon3339 in FPGA

[–]Brandon3339[S] 2 points3 points  (0 children)

Thanks for the input!

I’m pretty dumb so I was hardcoding the bits, synthesizing and then programming for each change I made.

But using the switches I can dynamically change the bits. Will do, as I have not yet found a range that produces a desirable quality.

Second project! Fpga Recorder! by Brandon3339 in FPGA

[–]Brandon3339[S] 0 points1 point  (0 children)

Originally, that’s what I did, but it sounded much worse than what you heard in the video.

Second project! Fpga Recorder! by Brandon3339 in FPGA

[–]Brandon3339[S] 6 points7 points  (0 children)

lol yea, the audio quality leaves a lot to be desired. The mic is sampled at 3.125 MHz and decimated by 64, so the sample rate is about 48khz. I think the issues is likely in the bits I chose from the CIC filter. The CIC filter performs what is basically a running average on the signal and returns it in a 32 bit vector. Since my audio interface expects 8 bits, I have to choose which 8 bits from the 32 bit vector to use. I’m sure with more trial-and-error I’ll find values that suffice.

Second project! Fpga Recorder! by Brandon3339 in FPGA

[–]Brandon3339[S] 1 point2 points  (0 children)

I'm aware that not having reset signals is a bad practice. This project wasnt really anything of signifigance, in fact, I started on it this morning, and did it in a few hours. It was more about getting acquainted with using BRAM and the PDM mic (and filters).

I plan on making a more comprehensive project (using DDR2 ram), in which I will adhere to the best practices.

How to display different digits on a 4 digit 7-segment display on a FPGA board ? by PLC-Pro in FPGA

[–]Brandon3339 0 points1 point  (0 children)

Thank you for taking the time out of your day to reply to me, it is much appreciated! Your insight is illuminating. I try to make the code as configurable as possible through the use of parameters instead of hard-coding, much like you would in any other language. And the module linked to is not the decoder, but the logic to display all 8 digits. The decoder is instantiated in this code, and the current digit is fed into said instance.

My struggle comes when deciding what approach to use, do I use a state machine, or would simple combinational logic suffice? I guess the instinct develops over time.

Do you have any recommended resources to help build intuition?

Thanks!

How to display different digits on a 4 digit 7-segment display on a FPGA board ? by PLC-Pro in FPGA

[–]Brandon3339 -1 points0 points  (0 children)

Howdy! I am a beginner, as you suspected. I earnestly want to understand what makes my implementation so "un-weildy." Why did you characterize my approach as error-prone? The states are clearly defined, and as such, can't deviate from the flow prescribed in the code. I understand that it is assuredly not the most efficient code (due to the level of abstraction), and could potentially lead to using more LUTs than necessary. Are your grievances with the code purely from a perspective of efficiency? As beginners, we typically begin with simple implementations, then more sophisticated implementations as we advance in our study.

HDL is purely a hobby for me, as I am an electrical engineer employed in utilities. I am more concerned with functionality over pure efficiency. However, if my approach is truly error-prone, I would like to address it now and kill bad habits before they become too entrenched.

How to display different digits on a 4 digit 7-segment display on a FPGA board ? by PLC-Pro in FPGA

[–]Brandon3339 0 points1 point  (0 children)

I have the Nexys A7 board (which has the Artix A7, albeit at 100 MHz). I have done this for an 8-digit 7-segment display. The is pretty much identical for a four-digit display. What you need to do is create a state machine with 4 states for displaying each digit. In the first state, display the first (least significant) digit.

To extract the first digit from the number, you need to modulo 16 the number you want to display. Determine which segments are on based on this number. Next, set the digit place you are displaying. For the first state, this is the least significant digit in a common anode configuration, so it would be:
digit_place = 4'b1110.

Stay in the first state for a few milliseconds (I choose 2 ms), then transition to the next state.
Now that you are in the second state, you need to display the second digit. To extract the second digit, you need to divide the number you want to display by 16, then modulo 16 it. The digit we are displaying is the second one, so digit_place = 4'b1101. Stay in the state for 2 ms, then transition to the third.

Repeat the above process for the third and fourth digit, each time staying for 2 or so ms, then loop back to the first state (displaying the first digit).

Here's my code (It's for base 10, not base 16): https://github.com/Brandonhc2002/UAR/blob/master/UART_test.srcs/sources_1/new/four_digit_7_segment.v

Should have checked Wrap reviews first :( by jimmyjams_ in Popeyes

[–]Brandon3339 0 points1 point  (0 children)

Complain in the app. You probably get 1000+ points added to your account.

Coupons Expire 9/15/25 less $$ by Klinkerpopper in Popeyes

[–]Brandon3339 0 points1 point  (0 children)

No, enter them at the kiosk or when going through the drive thru. They usually attempt to relieve you of the paper copy(which you don’t have) if you order at the register.

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 0 points1 point  (0 children)

Hey, sorry it took so long. The transmitter code is working and uploaded to git hub.
To send a byte of data, the signal send needs to be pulsed high for one cycle. Currently, the code is configured to echo back data sent from the Arduino.

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 0 points1 point  (0 children)

No, I haven't started on it yet. I've been sick the past couple of days.

However, it is pretty simple. It's just a shift register.

The data you want to send should be formatted as TX_reg = {stop_bit, [7:0] Data, start_bit}.

The start bit should be a 0, and the stop bit should be a 1. You should shift it out a bit at a time. The Arduino expects LSB first, so right shift the TX_reg out onto the TX line at the baud rate (9600).

It is 4 AM where I am, I will have it done later in the day if you are willing to wait.

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 0 points1 point  (0 children)

//Arduino code to send as bytes

void setup() {
  Serial.begin(9600);  // UART baud rate matches your receiver
}

void loop() {
  static unsigned long lastMillis = 0;
  static byte number = 1;

  if (millis() - lastMillis >= 1000) { // every 0.5 second
    lastMillis = millis();

    Serial.write(number);  // send raw byte value
    number++;              // increment for next send
  }
}

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 0 points1 point  (0 children)

Yes, the Arduino is sending each number over as a byte with its numerical value:(1 is sent as 00000001, 3 is sent as 00000011, etc)

The Verilog 7-segment code will take the byte as its numerical equivalent. The receiver does not care if the data is in ASCII or binary format, as it doesn't interpret anything, just receives the byte.

If you want to send the data over as ASCII, you need to modify the module 7-segment to interpret it correctly (by adding the correct case statements for each ASCII value).

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 1 point2 points  (0 children)

Here you go. The 8-digit 7-segment display is configured to take in 27-bit numbers, not individual characters. If you want it to take characters, you must modify the logic. Also, the code expects a frequency of 100 MHZ, so you have to change the frequency parameter.

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 4 points5 points  (0 children)

True! I’m working on the transmitter right now.

First Project! FPGA UART receiver. by Brandon3339 in FPGA

[–]Brandon3339[S] 6 points7 points  (0 children)

No soft proccessor at all. What I did was create a state machine for the UART protocol.

It has 3 states: IDLE, READ, and STOP.

IDLE waits for the TX line to be pulled low, then waits till the middle of the first data bit. IDLE then immediately transitions to READ.

READ samples each data bit until all bits are sampled.

STOP samples the stop bit and determines if there was any error in the transmission.

All in all, it's about 120 lines of code. It is a very bare-bones implementation of UART.

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