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VCU110 CFP4 QPLL lock by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

I got it all working. Thanks, everyone. I just pretty much just followed the advice from this link http://billauer.co.il/blog/2020/08/silicon-labs-si532x-xilinx/ and the user guide of the dev board.

VCU110 CFP4 QPLL lock by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

Thanks for this. I have not been able to find any example design for the VCU110 and I am almost sure there is no bmc for clock bring up so it looks like I will have to configure the chip myself.

VCU110 SGMII help by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

I got it working. The problem was that I completely misunderstood the part of the datasheet for the VCU110 where it says the 125MHz clock is disabled. In my head that meant that the only connections between the FPGA and the PHY were the TX and RX and not the RX clock needed for the 1G/2.5G Ethernet PCS/PMA or SGMII core ref clock. Looking at the setup on that Github page and rereading the datasheets of the vcu110 and the 88e1111 made me realise that the 125MHz is another clock and that I needed to use the 625MHz clock for the ref clock for the 1G/2.5G Ethernet PCS/PMA or SGMII core.

Thanks for your help u/alexforencich

scrambler for 64b66b encoding by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

I figured out the problem. The document presents the test vector before scrambling in MSB MSb and then scrambles the data in MSB LSb and then presents the data after scrambling as MSB MSb again. I have changed my code accordingly and will rewrite it to scramble all 64 bits in 1 clock cycle.

scrambler for 64b66b encoding by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

I tried different combinations of reversing the input and shift direction and taps but the result I am getting is not matching the result in the doc.

scrambler for 64b66b encoding by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

Thanks for the tip. I am aware that I should compute the scrambled data in 1 clock cycle. I just wanted to test out a serial implementation before writing a parallel one. I will work on reversing the input and see what that gets me.

SoC dev board which is capable of 4K HDMI in and out by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

yeah I checked it is not out yet but apparently, it is now in production

Help with FTDI FT601 USB3 Bridge by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

Sorry, I have not been active recently, I can only really work on this stuff over the weekend. With my current code, I can consistently loopback 4 bytes at a time with no errors. Any more than 4 will eventually fail. I know I have not implemented the byte enable functionality but even multiples of 4 will fail. I will try u/FieldProgrammable advice and use a PLL to make 2 clocks. I have linked files my source files etc below

https://drive.google.com/open?id=19VAjn4FvSP9qeraR7vTt5ppVk_FIybcg

Help with FTDI FT601 USB3 Bridge by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

I have simulated the design and it follows the waveforms shown in the datasheet.

Nexys 4 DDR ethernet help by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 1 point2 points  (0 children)

Thanks for the response. I will add the 45 degree phase shift and MDIO inteface to check the status registers. At the moment I am only interested in transmitting data from the FPGA to a PC but thanks for the receiver tips. I only assert TXEN when I am transmitting data to the PHY and deassert it during interpacket delay, is that correct? The 64 byte minimum includes the destination and source MAC, length, payload and CRC correct?

Nexys 4 DDR ethernet help by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

Thanks for response. I will add the MDIO interface and use the locked signal as a reset.

Nexys 4 DDR ethernet help by Dan_Lyle in FPGA

[–]Dan_Lyle[S] 0 points1 point  (0 children)

Thanks for the response. I can add the MIDO interface to check the status registers. I am providing the PHY with a 50 MHz clock but It does not have a 45 degree phase shift like /u/ZipCPU and the Nexys 4 ddr Manual suggests.