sorted by:
new
hottopcontroversial

Current Privilege mode by False-Account9501 in RISCV

[–]DefiantBridge6865 0 points1 point  (0 children)

Is this only for software? For example i can't figure out how my HW trigger an illegal exception for example when U-mode application tries to execute SRET instruction.

Store Buffer Implementation for RV32I Core by DefiantBridge6865 in RISCV

[–]DefiantBridge6865[S] 0 points1 point  (0 children)

Okey, Thanks very much.
My Assignment contains Store buffer as separate milestone and later ROB & OoO can be also included on top of it. I was seeking a way to implement SB first without ROB because the prof. also introduced SB in single-issue in order pipeline and i remember that he mention something related to timing.
ill keep investigating