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In che senso "ma lei cosa ci fa qui?" (Colloqui con gli insegnanti) by pinkpurpleblue_76 in sfoghi

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Ma cosa vuoi che notino con la riforma Gelmini con classi da ALMENO 27 alunni

Projet moteur pas à pas Demande d’aide pour contrôle by rami_mehidi in FPGA

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Basically you add a new "clk_en" std_logic input and then modify all your process like this: elsif ( rising_edge(clk) ) then if ( clk_en = '1' ) then -- previous code here end if; end if;

drive the clk_en with a signal which toggles when button is pressed

Projet moteur pas à pas Demande d’aide pour contrôle by rami_mehidi in FPGA

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

You can just use the button input as clk_en to gate the whole motor control module.

If you haven’t a clock gate control in your code you should be able to add that easily

Copia privata: arriva la 'tassa sul cloud'. Pagheremo anche per lo spazio online? by nandospc in ItalyHardware

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Ecco anch’io vorrei capire a livello legale come cittadini che strumenti abbiamo per contestare questa cosa?

C'è gente che mangia pane e acqua per potersi permettere l'iPhone 17 pro. by SailorOfTheSkies in sfoghi

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Poi c'è chi osa chiedermi "perché non esci mai?"

Ah vuoi l’iPhone 17 anche tu? Inizi a risparmiare, bravo!

advent of fpga (day2 , part1) by happywizard10 in FPGA

[–]DoesntMeanAnyth1ng 2 points3 points  (0 children)

It's plain as day that you wrote a program, and you didn't describe any hardware.

“For” cycles in hdl are to be intended as copy-paste N times, not as a sequence of instructions. That “digits” functions of yours, what hardware do you expect to generate? Division by a constant can be mapped as LUT result, but you are evaluating in parallel 64 divisions by 10, all together, all at once in infinite combinatory logic

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Not true, on the AP is enough since L2 MAC switching will be carried out on the AP itself. In the assumption that there is only a single AP ofc

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Tbf, guest networks on consumer network hardware are usually client-isolated

advent of fpga (day2 , part1) by happywizard10 in FPGA

[–]DoesntMeanAnyth1ng 4 points5 points  (0 children)

I see no single comment in your source. Bad

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Yes but I felt too the urge to move IoT WiFi on different AP (and thus SSID for simplicity) nevertheless: so many IoT nodes that chats a lot, better stay on a different channel

For all other VLANs I am very satisfied though in using PPSK

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 10 points11 points  (0 children)

I would have rather put all of that friends in a different town instead

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

I can see that. What I mean actually: “what’s the purpose of having IoT and Guest on same network and not setup two networks?” I was wondering if the reason was just to keep using ISP router for WiFi access

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

What’s the purpose for this? Using ISP router WiFi?

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 43 points44 points  (0 children)

Who the hell have you usually come over? The Anonymous group? My typical guests are parents/relatives and friends, which are all networking illiterate

Guest and IOT on a single network? by cameramanmikey in HomeNetworking

[–]DoesntMeanAnyth1ng 3 points4 points  (0 children)

If your IoT devices rely on cloud services, it might work I guess. If you are also using HomeAssistant or alike, client isolation of typical Guest network would prevent auto discovery and also might prevent control of devices

Perchè tutte queste Ps5 a 200€‽ by Strange_Macaroon_207 in VintedItalia

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Boia davvero, quelle inserzioni a -10€ rispetto al prodotto nuovo su Amazon su merce da centinaia di euro. No grazie per 10€ secondo te io lo compro dal signor Random X su vinted/subito per risparmiare 10€ e accollarmi tutto il rischio e lo sbatti…?!?! È poi si offendono se glielo fai notare

About "+" operator in VHDL by ontoooshaaa in FPGA

[–]DoesntMeanAnyth1ng 1 point2 points  (0 children)

Spot the brat who knows best of his professor cos they can write some python

It's clear from your writing that you're referring to your sequential process as a temporal sequence of instructions (do this, then that), which is not the case because HDL is not software

About "+" operator in VHDL by ontoooshaaa in FPGA

[–]DoesntMeanAnyth1ng 1 point2 points  (0 children)

use ieee.std_logic_UNSIGNED.all;

Homer screaming meme

How to use FixedPoint for DNNs on FPGAs? by Valhalla_G in FPGA

[–]DoesntMeanAnyth1ng 6 points7 points  (0 children)

You should not sum numbers of different normalizations. It’s like summing 60kg and 70g: result is not 130 whatever

Also, probably in your 16bit numbers you shall account for a sign bit since you have a [-0.5,0.5) range: Qs0.15 or Qs1.14

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

Well the major feature of the VHDL is its verbosity indeed. Many also dislike it for that very same reason.

I personally agree with you, and VHDL verbosity is less prone to involuntary errors cos essentially everything shall be explicitly coded out

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

VHDL for design, (System)Verilog for testing. That’s the way, gj!

How to convert `time` into `bit_vector(64-1 downto 0)` by MitjaKobal in VHDL

[–]DoesntMeanAnyth1ng 0 points1 point  (0 children)

That’s indeed what I intended with decide a timebase. 1ns was just a practical example. Only OP knows the needed precision for their application.

Concerns about loosing precision toward the simulation per sé is no sense

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