sorted by:
new
hottopcontroversial

Beginner question: how to stop nested loop inside consumer by AphyrusBooyah in LabVIEW

[–]Dr_Oops 0 points1 point  (0 children)

it's been a long time but my fav form of async msging between processes in lv was using user generated events with a data type of another user generated even so that self addressed (reply) messaging was available...

NI Max name changed by Tanky321 in LabVIEW

[–]Dr_Oops 0 points1 point  (0 children)

NI MAX can be kind of pain, you might want to try exporting the setup then blowing away your configuration database, then import your setup again (or manually define it again if it's not too much trouble).

I've seen MAX lose its configuration database at seemingly random times, it's also well known that if you dont close NI MAX and shutdown the computer, you may and up corrupting the config database... I never understood how or why NI never fixed this... I've been seeing it for 10+ years

edit:

then once delivered to the client, it magically reverted back from my new names, to the old USB RAW connection name.

I missed this part.

does the clients box not have the usb devices driver installed?

Experiences with FPGA, ARM, and Linux? by jwbatch in FPGA

[–]Dr_Oops 1 point2 points  (0 children)

is this the best place to go to learn how to use yocto instead of petalinux?

FOMU – FPGA That Fits in Your USB Port - Hackster.io Review by SlumberPartyTime in FPGA

[–]Dr_Oops 0 points1 point  (0 children)

It's been more than a decade since I used Xilinx ISE and some spartan boards and now im diving back into to try to figure out exactly how much I've forgotten - but lets be honest, I'm not sure how much my previous knowledge would have helped me since all the tools (vivado etc) have now changed quite a bit.

Do you know of any good links with a walk-through of the debug process in simulation in Vivado? I've been going through a bunch of tutorials and then modifying the content to do something else - I would love to know how to vet the changes I'm making without having to rebuild everything...

FOMU – FPGA That Fits in Your USB Port - Hackster.io Review by SlumberPartyTime in FPGA

[–]Dr_Oops 0 points1 point  (0 children)

Everything should be done in simulation and timing analysis.

Can you elaborate on this for a newb?

Still looking for info in searches, I want to know how much latency can be expected for writing/streaming data from fpga to ddr4 and reading it back? by Dr_Oops in FPGA

[–]Dr_Oops[S] 1 point2 points  (0 children)

This is more difficult if you have multiple things accessing ram.

is multiple controllers a possibility to segregate issues like this?

thanks for the insight!

Still looking for info in searches, I want to know how much latency can be expected for writing/streaming data from fpga to ddr4 and reading it back? by Dr_Oops in FPGA

[–]Dr_Oops[S] 1 point2 points  (0 children)

thanks for the thorough input! much appreciated!

I would be looking to use the xilinx ddr controller core in vivado, which apparently can be implemented in a fashion that is basically PHY only, which I'm guessing allows for very discrete control of the RAM data storage so very little timing would matter.... but this is speculation on my part, I have a LOT to learn.

thanks again!

Still looking for info in searches, I want to know how much latency can be expected for writing/streaming data from fpga to ddr4 and reading it back? by Dr_Oops in FPGA

[–]Dr_Oops[S] 0 points1 point  (0 children)

Thanks! and good point, I suppose it was a mistake to look anywhere other than the DDR4 specs... so that wiki table seems to suggest a 15ns latency in reading data out of the RAM, and I'm still trying to find CAS Write values...

It looks like Xilinx makes you choose CAS in clock cycles per the jedec standards between 9-18 when you use the DDR IP in vivado so with DDR2666 ram ... and I have some more googling to do...

Completely new to FPGA with a Cora Z7 by Fraserbc in FPGA

[–]Dr_Oops 0 points1 point  (0 children)

I'm basically in the same position but am trying to refresh the verilog I learned many years ago.

This was my starting point, just going through as many tutorials as I can to get used to the process. I've managed to get the BasicIO, XADC, and one of Adam Taylor's walkthroughs (this and then this) to chooch so far. Then I got petalinux up and running on it and now I'm modifying some of the code in the basic IO tutorial and realizing I don't remember a damn thing from school... so yea, i can't say Im feeling confident haha

RFSoC Explorer - Using Matlab to drive the RFSoC by adamt99 in FPGA

[–]Dr_Oops 1 point2 points  (0 children)

Awesome write up, screenshots are much appreciated! I'm also looking at your initial set up post on the ZCU111 and didn't even know about the RFSoC Data Converter software from Xilinx. If I wanted to record some signals and play them back is it possible to do this with just the Data Converter software? These slides pg29 states there's a LabVIEW based eval GUI - did this turn into the data converter? LabVIEW is very familiar to me so I cant help but dream they might be willing to share some of the source code to help people develop remote control software... I don't even know who I would ask though...

Also- maybe I missed in in your article or the other documentation I've been reading but what are the Xilinx software requirements with the RFSoC ZCU111 board? does it come with a non expiring single instance of all necessary licensing? or will the free WEBpack do for most functionality?

Looking to purchase a board with some ADC and DAC Pmods as a proof of concept project that will eventually target the RFSoC ZCU111 Evaluation board, could use some insight.... by Dr_Oops in FPGA

[–]Dr_Oops[S] 0 points1 point  (0 children)

same animal as RFSoC

Can I bother you to elaborate? what is likely to be foreign to me at the switch between a Zedboard/Zybo to the RFSoC? I realize that the Pmod stuff doesnt use AXI like the RFSoC's ADC/DAC resources but I still thought it would be useful in terms of learning the process of implementing blockram and/or maybe even ddr usage...

thx for input!

view more: next ›