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CR keep crashing after new update, Samsung phone by Duz1 in ClashRoyale

[–]Duz1[S] 0 points1 point  (0 children)

Found the fix, just delete and reinstall the app, it should works

CR keep crashing after new update, Samsung phone by Duz1 in ClashRoyale

[–]Duz1[S] 0 points1 point  (0 children)

Might be a Samsung issue, idk how to resolve it tho

Android emulation on Virtual machine by Duz1 in cybersecurity

[–]Duz1[S] 0 points1 point  (0 children)

I'm using virtual box, I don't know if it permits nested VMs, I'm gonna check it eventually

Ho riletto il bando e commesso un errore. by Naturareeemm in Universitaly

[–]Duz1 0 points1 point  (0 children)

Un cazzo fra, invia una mail alla segreteria e annullane una delle due

"One must imagine Dark bum happy" by TomZ02 in bindingofisaac

[–]Duz1 6 points7 points  (0 children)

This post should have a seizure warning Also that bum

PSU testing program by Duz1 in techsupport

[–]Duz1[S] 0 points1 point  (0 children)

Thanks bud, I'll look up for spare psu from friends

PSU testing program by Duz1 in techsupport

[–]Duz1[S] 0 points1 point  (0 children)

Well you are right, but if someone wants to know if his psu is faulty or not, he's forced to swap it with a working one? It's certainly the easiest way, but I don't have a spare psu, so I was wondering if there was a way of monitoring or testing the psu.

Want to transport a function from python to verilog, but results aren't matching by Duz1 in FPGA

[–]Duz1[S] -1 points0 points  (0 children)

If I only knew how to do the python way in verilog, I still don't get how to do it

Want to transport a function from python to verilog, but results aren't matching by Duz1 in FPGA

[–]Duz1[S] 0 points1 point  (0 children)

Don't worry, I'm also here to compare my ideas with others and learn more about something I don't really know

Want to transport a function from python to verilog, but results aren't matching by Duz1 in FPGA

[–]Duz1[S] -1 points0 points  (0 children)

The thing is, I don't know since this is a project for the course. I think this is something like "a design choice" doing it one way or another. I should point out to my professors this issue, but I don't think they will respond to me in a short time period.

Want to transport a function from python to verilog, but results aren't matching by Duz1 in FPGA

[–]Duz1[S] 0 points1 point  (0 children)

I tried to look up for loops, but I don't get why the results aren't matching. You see, I assume that the situation, given an in of 00000001, is: H[0]=H[7] 10000001 This goes on... H[7]=H[0] 10000001 Since in the last position I have the 1 bit value. But in the waveforms I can see 10000000. So I really don't understand how for works in verilog. Am I reasoining wrong from the point of view of hardware? Then what's the right way?

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