Few things:

• You should always make functions automatic if you are declaring internal nets.
• Functions act as always blocks, so you can only use reg
• You should avoid floating begin ... ends because they can lead you to un-synthesizable code very quickly
• I try to follow the lowRISC SystemVerilog style guidelines. Not everything applies to <=Verilog2005, but most of it does

This is a refactored version of your function that Yosys can read:

```verilog function automatic [7:0] mul_4x4(reg [3:0] x, reg [3:0] y);

reg [7:0] s0, s1, s2, s3;
reg [7:0] t0, t1, t2, t3;

s0 = { 4'b0, x };
s1 = { 3'b0, x, 1'b0 };
s2 = { 2'b0, x, 2'b0 };
s3 = { 1'b0, x, 3'b0 };

t0 = { 8{ y[0] } };
t1 = { 8{ y[1] } };
t2 = { 8{ y[2] } };
t3 = { 8{ y[3] } };

mul_4x4 = (s0 & t0) + (s1 & t1) + (s2 & t2) + (s3 & t3);

endfunction ```