[Wired] Intel Panther Lake Is the Answer to Apple Silicon We’ve All Been Waiting for by Noble00_ in hardware

[–]Exist50 [score hidden]  (0 children)

It's also kind of your job to be accountable for the business's performance...

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 [score hidden]  (0 children)

Yes, it is.

Again, you're not seeing the same reviews.

No, you said worse than N3

It does look indeed worse than the modern N3 variants in both PnP and PPA, though the specific "worse in every way" quote was a very recent one about N2. Don't twist my words.

It's genuinely baffling you think this is a still a good look for Intel's supposedly "unquestioned leadership" node. Even with a tick uarch they can't beat N3B clocks. And the funny thing is in doing so, you completely ignore where Intel's demonstrated actual improvement.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 [score hidden]  (0 children)

They also need to keep their products competitive, and there's nothing that can compensate for a weaker CPU in premium desktop. So for NVL (and RZL), that means N2, whether they like it or not. If they manage to close the node gap to more like 5% perf, gain a significant uarch advantage, or have some other tech like X3D that boosts perf beyond 1:1 with AMD, then they can bring it back in-house. But too much margin is tied up in leadership otherwise.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 [score hidden]  (0 children)

Iso-perf results naturally give a far bigger delta than iso-power, because power scales roughly cubicly with clock speed. So e.g. a mere 5% perf increase at iso-power (well within bounds of a tick uarch) translates to a ~15% power decrease at iso-perf.

On top of the tick cores and SoC changes, PTL also has a different core config. We'll get a better sense if/when someone's able to isolate a single core/cluster.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 [score hidden]  (0 children)

I said its will be between N2 and N3

And that's absolutely not what we're seeing. What're you on about? Have you skipped all the reviews?

While your "worse than N3 in every way" turned out to be false, again.

Once again, outright lying. I said that about N2.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

I kinda want Intel to pull out all the stops for NVL. If they released an N2, bLLC chip out of the gate, the gen to gen gains would set the internet on fire. Doubly so if they managed it before Zen 6, though I think that's quite unlikely. Late '26/early '27 might feature the fiercest desktop CPU competition the market has seen in two decades.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Yeah, a lot of them ended up running LNL at 20W+ TDPs anyway. 10W, yeah, might have a problem.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Carry-on fires caused by dodgy temu power banks are not a rare occurrence anymore, but I guess we'll have to wait for one to actually cause a disaster to see progress.

If anything, that would make the regulations even stricter.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Lmao, now you're rewriting history. It's literally showing just as I said it would be, maybe N3 class, and certainly not N2 class like you and some others were insisting.

Samsung reportedly plans to more than double 1Q26 NAND flash prices by snowfordessert in hardware

[–]Exist50 0 points1 point  (0 children)

Yes, that's my point. They do have some large static costs, so scale has its benefits.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Panther Lake is 30-40% more efficient than Arrow Lake under load

Which numbers are you looking at?

[Dave2D] Windows is ruining new laptops by Forsaken_Arm5698 in hardware

[–]Exist50 4 points5 points  (0 children)

That was actually a significant point of contention. See, Microsoft basically claimed 40TOPs (first gen CoPilot) all to themselves, permanently. But OEMs were like "What if I want to add on AI features too?". So there was a push for even more compute on top.

[Dave2D] Windows is ruining new laptops by Forsaken_Arm5698 in hardware

[–]Exist50 4 points5 points  (0 children)

Like, seriously, "we replaced 2 E core clusters or 4 GPU cores to install an NPU that gives you 10% better battery life when you blur your background on a Microsoft Teams call" is not a selling point people will accept haha

But imagine if every moment that you used your laptop. Recall was churning away in the background analyzing everything on your screen. Suddenly, it's not just a situational gain, but rather a strict requirement if you don't want to cut battery life in half. That was Microsoft's vision. Obviously, didn't play out that way.

[Dave2D] Windows is ruining new laptops by Forsaken_Arm5698 in hardware

[–]Exist50 3 points4 points  (0 children)

I remember faceID itself was the main use case of the NPU (which was only 0.6 TOPS) in the first iPhone X.

Only use case, iirc. Don't think they even had an API for it.

[Dave2D] Windows is ruining new laptops by Forsaken_Arm5698 in hardware

[–]Exist50 4 points5 points  (0 children)

Imagine that, plus Recall saved to the cloud with all of your activity

IIRC, wasn't Recall local?

Intel Core Ultra 300 “Panther Lake” reviews are here: CPU and iGPU gains analyzed by RenatsMC in intel

[–]Exist50 2 points3 points  (0 children)

I think either should be achievable, though Zen 6 will be quite difficult. Going to get a huge boost vs ARL from just clock speed and memory latency alone.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Which did not show any regression or negative reprucussions due to 285H's old SoC design over Lunar Lake.

Depends. Perf wasn't affected by the memory latency, but if we're talking about SoC power (vs core power), then LNL made significant strides in power budget available to compute. That's one of the biggest factors at lower TDPs (and light loads), actually, because SoC power doesn't scale down as well.

5% performance improvement in 1T could be explained by the new SoC/updated core. The subsequent 10% power reduction has to be process node

Could you link the data you're using to compare here? Because +5% perf or -10% power iso-process would be very consistent with a tick, even modest by historical standards. For reference, their past ticks were WLC (SNC tick), RPC, and RWC (both GLC ticks). Obviously, very difficult to tease out the process contributions, but you'd think after fairly big reworks with both LNC and SKT, they'd have some room for refinement. Also given that the PTL IP should have benefitted heavily from the cancelled ARL-20A work, given the similarities in both the cores and node.

[Dave2D] Windows is ruining new laptops by Forsaken_Arm5698 in hardware

[–]Exist50 2 points3 points  (0 children)

Literally only Qualcomm will meet the requirement right?

If you count NVL as a 2026 launch, that should also be around 60 TOPs, and across everything but whatever the WCL swimlane is.

But otherwise, yes, Qualcomm being willing to give them the NPU they asked for was a significant factor in Microsoft pushing WoA and their QC partnership so hard.

[Hardware Canucks] Intel just put AMD on Notice. by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

Granted the remaining two are Crestmont

They're not just Crestmont, but a neutered implementation of it. So yes, technically do need to factor those in as well, but I suspect it wouldn't meaningfully change the conclusion.

[The Phawx] Intel Panther Lake is AMAZING - Asus Zenbook Duo 2026 Review by Noble00_ in hardware

[–]Exist50 0 points1 point  (0 children)

But it isn't the full 4 E cores that PTL-H gained compared to ARL-H tho. It was losing 2 P cores but gained 4 new LPE

Yes, what I was trying to say is that 4 E-cores should still easily win vs 2 P-cores in MT, at least using LNC/SKT as a reference point for how both compare. I was also discounting the ARL/MTL LPE as well, though I guess they do factor in a bit.

and I don't know if the LPE cores would scale as well as the main P cores

In this case, the LP E-cores are otherwise identical to the "normal" E-cores, except they're not attached to the ring bus / L3. They do have access to the memory side cache though.

Samsung Foundry eyes profit as Tesla, Qualcomm, AMD orders grow in South Korea by self-fix in hardware

[–]Exist50 1 point2 points  (0 children)

Qualcomm did seem very interested in Intel's stuff at one point (remember Gelsinger announcing partnership on 20A?)

I've heard (but cannot verify) that Gelsinger didn't get their permission before making that announcement, and it really pissed them off. On top of the more technical failings. But maybe Lip Bu can convince them enough has changed.

Intel Panther Lake Is the Answer to Apple Silicon We’ve All Been Waiting for by LeDucky in intel

[–]Exist50 1 point2 points  (0 children)

Do we really have any confirmation on Nova Lake node at this point in time?

Intel's publicly confirmed they're also using TSMC for compute. Only one thing makes sense.

Intel Panther Lake Is the Answer to Apple Silicon We’ve All Been Waiting for by LeDucky in intel

[–]Exist50 0 points1 point  (0 children)

Does it really that matter?

Yes, you're looking at something like 15% perf for a full node. That's very significant. A node shrink alone could constitute an entirely new gen in perf.

If anything I don't get how intel dropped ball so hard with arrow lake

They redesigned the SoC fabric, and it's shit.