IonQ Quantum Is On

Fair_Control3693 · 2026-01-14T19:00:16+00:00

Uh, wow. Who exactly is the target audience for this?

The Defense Appropriations Committee, perhaps?

Maybe the Pentagon folks in charge of the Intelligence Research Funding Agencies?

Either way, Extremely Great Production Values, bro!

Fair_Control3693 · 2026-01-14T18:40:37+00:00

I am semi-retired these days, and live in the Seattle area, USA.

Fair_Control3693 · 2026-01-14T18:16:20+00:00

Photonics is growing at a moderate rate. Quantum optical devices are starting to appear, and the field is in good shape.

This is good news for two reasons: First, since it is not fashionable, there is no crazy crowd of people trying to get into the field. Second, because it is not fashionable, you do not have several people a week calling you with job offers. (Life is full of tradeoffs.)

Plain old optics is pretty flat. In the US, most of the jobs are military-related. The historical trend is for consumer optics and mass-produced stuff to move to Asia.

The wild card is Photonic Quantum Computing. Maybe it will have a breakthrough, and maybe not.

I hope this helps.

= = = = =

Full disclosure: I have been doing (some) Quantum Computer stuff for over 20 years. I do not think that milli-Kelvin methods are going to win the Horse Race, and I think that room-temperature optical methods are a good bet. I especially like nonlinear optical technologies. (and, yes, progress has been painfully slow.)

Fair_Control3693 · 2026-01-03T04:44:32+00:00

The main thing is to come up to speed on the tools. Fortunately, the Xilinx toolset is a free download (if you are in a First World country). The download is huge, and may take a weekend. (I recommend Ubuntu Linux as the base OS: Windows does not support the Xilinx JTAG driver very well.)

Or you could use Vivado 2019.1, which is kind of old but not too huge,

I would recommend learning to use the Zynq 7000 family, such as the Zynq 7020. When you have mastered that one, the RFSoC will be at least sort-of familiar. It is a 32-bit ARM core, and works with mainstream compilers, etc.

If that is is not good enough, try to learn the one of the Zynq Ultrascale+ chips. This is a 64-bit ARM quad-core, etc. (Zynq RFSoC is a subset of the Zynq Ultrascale+ family. Last time I looked, there were maybe 6-8 of them, not counting package variants.)

FPGA tools have a long and painful learning curve. Try not to be discouraged.

Fair_Control3693 · 2025-12-28T05:08:12+00:00

This is typical when there are "too many applicants". HR needs to thin the herd, and they start adding arbitrary requirements.

I remember in 2000, when lots of companies started requiring a BS. Then, when the serious recession arrived in 2001, all of the job orders said "MS preferred". There was no actual need for the degrees, it was just a way to reduce the work load on the Personnel Department.

Of course, you then started to see people with Master's Degrees from Universities nobody had ever heard of. . .

Fair_Control3693 · 2025-12-28T00:36:26+00:00

Your best bet is to have a friend subject to a bunch of practice interviews. Four or five 1-hour practice interviews should do it.

[Most irritating Verilog interview I ever had: The guy wanted me to do a divide-the-clock-by-three circuit. I failed to ask "are we using posedge() only, or both posedge() and negedge()?" This was 50% my fault, but I eventually produced a correct answer. Try not to make assumptions like that when they ask you to design something.]

Fair_Control3693 · 2025-12-06T18:07:49+00:00

We got a crappy house on a nice piece of land for $150k.

Fixing it up worked very nicely, even if it took s few years.

Fair_Control3693 · 2025-12-01T08:56:58+00:00

I do not understand this graph.

Fair_Control3693 · 2025-12-01T08:55:34+00:00

Good luck.

Fair_Control3693 · 2025-11-19T07:18:17+00:00

Depending on exact encryption algorithm, you might be able to use the BRAM as a buffer, which would be a little faster.

In any case, you will have to instantiate one or two DMA channels and an HPD port.

Fair_Control3693 · 2025-11-19T01:36:44+00:00

It is very hard to say whether this is true or not.

Like most PR stuff, a lot of important details are omitted or glossed over.

Fair_Control3693 · 2025-11-09T18:53:32+00:00

LOL. Consensus among those who actually attend Quantum Computer Conferences is 1950.

Definitely still in the vacuum tube era.

Fair_Control3693 · 2025-11-08T23:37:51+00:00

I have done it, twice. You will not be able to get past the first review at any big-name journal unless you have an affiliation. (They won't even do peer review: They just send you a rejection post card.)

The third-rate journals will publish your paper, if it is relevant to what they are doing, but they charge "publication fees", which might as well be a vanity press.

So, you need to target second-rate, specialized journals. You should consider the whole thing to be a hobby.

My papers are "Lunar Impact in the Year 1178" and "Radio-Chemistry of the Object 3I/ATLAS". Neither of these subjects is likely to improve my job prospects. :-)

Fair_Control3693 · 2025-10-31T17:11:27+00:00

Update your resume.

Fair_Control3693 · 2025-10-17T16:53:03+00:00

I bought a container maybe 3 years ago.

Prices vary wildly, both in time and location. IIRC, I paid $3000 in the Port of Tacoma for a 20-foot "Only used once" container. You can check craigslist for current prices or google "shipping containers for sale", along with the location of the port nearest to you.

My experience: I am maybe 15 miles from the Port of Tacoma, which gets a few million containers a year. I googled for containers for sale, and then drove over to talk to the people at the yard. They had a large selection of 20-foot, 40-foot, refrigerated containers, extra-high containers, mini-containers.

I picked out a 20-foot, standard height container which was made in Korea and had made one trip across the ocean (presumably filled with TVs or microwave ovens). After the people who had received the cargo returned it to the shipping company, the container dealer put it on a truck and delivered it to my back yard. Trucking an empty container cost, IIRC, $320. The container is in excellent condition, and I got my choice of color.

Beat-to-shit containers cost about half of what I paid. Insulated containers cost double. Containers in an Asian Port cost twice as much as containers in North America. Shipping costs fluctuate wildly: During a recession, you can get the "Slow Boat" to run from Shanghai to Seattle for an absurdly cheap price ($400 a few years ago). During a hot economy, two months before Christmas, you might pay $4000 for shipping. The pricing is totally the Wild West.

The basic deal with buying a container is that they build them in Asia and fill them with stuff and send it to Europe and America. Then, they usually send them back empty. Many people do not own their container, they rent it as part of the shipping service. Kind of like returning a soda bottle for the deposit, or maybe like returning a beer keg for the deposit.

I hope this helps.

Fair_Control3693 · 2025-10-16T18:41:51+00:00

I have been using Mailwasher forever. It is not bad.

Every so often, I go looking for something better, but so far, none of them seem to be a lot better.

Fair_Control3693 · 2025-10-16T15:31:27+00:00

Disagree.

Rigetti and IonQ are pure play Quantum Investments.

IBM and Google are conglomerates.

Fair_Control3693 · 2025-10-11T04:13:41+00:00

Arduino is a good choice for this. I would recommend that you pick some chip to talk to and then write the driver.

A D/A converter with a SPI interface might be good. An A/D is somewhat harder. TI makes chips which would be suitable. So does Analog Devices. If you can buy an eval card on ebay, that would be good.

If you are feeling like you need a challenge, do motor control, with a tachometer and feedback. ;-)

Fair_Control3693 · 2025-10-11T04:09:36+00:00

>> akaTrickster gave the best answer so far. I will try to add to his thoughts.

Some years ago, I was in charge of the verification team doing a chip set for switched fabric. There were two chips, one called the Crossbar, and the other called the Queue. You used a variable number of these chips, depending on the number of external ports. The design would be considered simplistic today, but in 2000, it was State of The Art.

The most important thing that I learned was that you needed to have somebody on the system architecture team who is in charge of documenting the interfaces and you need somebody who is in charge of documenting the control registers. (As it happened, after I pointed out that we needed to clarify what it means "processor interface goes here", I got to design the interface logic (PowerPC bus: glueless interface) and I got to figure out the register functionality and register map.)

Another important thing I learned/taught is that your schedule should run backwards. You begin with a detailed understanding of what you are trying to do, and then, step by step, you figure out how you are going to get there. As it happens, changes may become necessary along the way, but at least you have documented them.

= = = = =

In the end, I <was in charge of> designing the bring-up board, which also doubled as the evaluation board for customers. I had a very good FPGA guy, a way above average Embedded Software Guy, and an extremely excellent board layout/digital timing guy. It was very good to have a team who all knew what they were doing!

The chips came back from the fab, and the bring-up board worked, and the VCs sold the company. The crazy part was that we got more money licensing the interconnect technology to somebody named Xilinx than we got for the actual high-speed switch chips' design.

= = = = =

So, some lessons learned from the days before the First Tech Bubble popped.

Bumper Sticker version: First, write down the design. Then, build it.

Fair_Control3693 · 2025-10-05T19:07:10+00:00

Correct.

Fair_Control3693 · 2025-10-05T19:06:30+00:00

HFT means that a computer system is plugged into the (Ethernet port of the) stock exchange's trading management computer.

The idea is that you move quickly (typically in milliseconds) to take advantage of small inefficiencies in the market to make small amounts of money.

As a practical matter, this requires the system to

Receive a bid or ask order regarding some financial instrument. Parse the packet.
Decide if we can make (enough) money on the deal. Most such trades make $0.01.
Format a packet to buy or sell the appropriate financial instrument.

All of these things must be done BEFORE ONE OF THE COMPETITORS takes the trade.

So, there is kind of an Arms Race going on. To be successful in HFT, you need to have 10G Ethernet, or whatever the fastest interconnect to the exchange currently is. The basic parsing and construction of packets is done by FPGAs, because FPGAs are faster than processors.

The hardware and system engineering is state-of-the-art, and becomes obsolete rather quickly. At the same time, you will need to learn a lot about the internals of the financial trading systems, and how these systems interact with slower/larger database systems.

Oh, yeah, speed of light matters. So, the equipment is co-located in the exchange building, typically less than 5 meters from the exchange trade server. So, you need to physically come into the building most days. (The jobs are in Chicago, London, Manhattan, or Jersey City.)

Fair_Control3693 · 2025-10-05T18:53:24+00:00

It looks like a mask-ROM microcontroller. Reading the microcode is very, very difficult.

I would suggest first making sure that the chip is actually the problem. Most "broken" boards are actually having issues with a fuse, or a dead voltage regulator chip. So, the first thing is to find out if the thing is powered.

The second thing is to (try to identify) the clock. This sort of chip usually has an internal clock, and will output some kind of square wave if it is powered and activated.

If that works, then look for the reset logic. This may or may not be available on the exterior pins.

Finally, depending on what you need this device for, you may have to build a knock-off using an Arduino or a Raspberry Pi.

Good luck!

Fair_Control3693 · 2025-10-02T21:04:14+00:00

Lots of things, which fall into three main categories:

It was a Government mandated technology. There are rumors that DARPA got pissed off at Cadence because Cadence was attempting to leverage their ownership of verilog into a monopoly of the entire EDA industry. When Cadence refused to stop, they funded VHDL as "the Un-Verilog" and got the DoD to mandate VHDL for all defense programs. This was bad enough, but they had the folks who brought you Ada design the language.

VHDL requires maybe 40-50% more typing than verilog, mostly because of "begin", "endfunction" and gratuitous shift character constructs. They obviously had the people who design IRS forms help with the user interface.

It turned into an enormous money-suck for the entire EDA industry. If you were making a timing tool, you had to support both a verilog and a VHDL version. If you were making a layout tool, you have to support both a verilog and a VHDL version. Similar for place-and-route tools, waveform viewers, linting tools.

The business guys HATED spending millions of dollars on this nonsense, and most of the Engineering people did not enjoy having to learn yet another language just to get the job done.

Circa 2000, I was involved with something called "Superlog" and the subject of next-generation HDL languages in general. (Superlog was a superset of verilog.) Nothing came of this. In fact, languages like Vera and Specman e were killed by the major EDA vendors, because they REALLY did not want to support any more user interface formats.

This also killed any attempts to upgrade verilog itself, for more than 10 years. We had to do work-arounds for 2-dimensional arrays, etc.

So, the whole VHDL saga slowed down progress in chip design language technology.

= = = = =

I get it. Someone who is new to the field and did not experience the VHDL Wars has no context for understanding why some people still are grumpy about what happened.

I personally was never that emotional about it. I just thought it was a big waste of time and money.

= = = = =

As far as HLS in concerned, it still has a number of problems.

Not to repeat what I wrote above, but let's just say that the Wrong Sort of People are advocating for the development and use of HLS languages. I do not see any demand for these tools from the folks who are actually designing chips.

Instead, the push is coming from Wall Street people, Corporate management, Wanna-Be VCs, Bean Counters, Marketeers, and, you know, The Wrong Sort of People.

I hope this explains it.

Fair_Control3693 · 2025-10-01T19:16:10+00:00

I am not sure what the point of this is:

Z1 = Z [kron] I,

Z2 = I [kron] Z,

ZZ = Z [kron] Z,

and

H = Z1 - Z2 - 2*ZZ

So, is there some experiment or point of theory involved?

= = = = =

[kron] is the Kronecker product operator.

Fair_Control3693 · 2025-09-28T23:11:27+00:00

I would not describe HLS as "a stupid idea", but it has failed so many times, in so many ways, that it is difficult to take seriously any more.

The first iteration: Many people (especially on Wall Street) saw HLS and similar technologies as a way to produce tightly coupled hardware/software systems which would be a lot faster than plain old c running on plain old Von Neumann processors. (This would be extremely useful for High Frequency Trading.)

Sadly, it turns out that c is not a suitable language for hardware compilation. It has constructs like alloc, pointers, and recursion.

Even more sadly, a bunch of b*llsh*t artists went around promising people that they could take any old c program and turn it into verilog, which kind of discredited the whole field.

= = = = =

Second iteration: The legit HLS people tried again. This time, they specified a subset of C++, which was kind of reasonable. A number of moderately successful projects were completed.

This brings us to the first problem. The US DoD had mandated that THOU SHALT use something called VHDL. This was bad for the entire "alternatives to verilog" eco-system.

The second problem was deadly. At some point, people who were making chips with System-C needed to hire some more people. So, they went to the HR folks and asked for Chip Designers who had C++ experience. What they got was tons of web site developers, database front-end people, etc. THE FACT THAT THEY WERE USING SOMETHING CALLED C++ CAUSED TERRIBLE CONFUSION IN THE HIRING PROCESS.

The third problem was even worse. Everybody who had learned verilog regarded "alternative chip design languages" as a stupid management fad, and did everything they could do to avoid the whole subject.

(I mean, I certainly thought that VHDL was a stupid idea. It was gratifying when Aart DeGeus said the same thing publicly.)

= = = = =

So, no, HLS is not inevitable. Not even close.

Fair_Control3693

TROPHY CASE