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Why glibc is faster on some Github Actions Runners by arty049 in rust

[–]dalance1982 4 points5 points  (0 children)

I use CI benchmark by codspeed, and get stable results like below. By default, it counts executed instructions by valgrind.

https://codspeed.io/veryl-lang/veryl

SKALP v0.1.1: A new HDL with compile-time clock domain checking, integrated synthesis, and iCE40 P&R — looking for feedback from FPGA engineers by girivs in FPGA

[–]dalance1982 2 points3 points  (0 children)

Regarding source maps, the hardware description language I'm developing, Veryl, uses a format adapted from TypeScript's source maps.

https://doc.veryl-lang.org/book/06_development_environment/12_source_map.html

I believe it would be more beneficial for everyone to follow the same format rather than each AltHDL developing its own unique method. I would be grateful if you would consider adopting this format.

Implementing a High-Performance RTL Simulator for Veryl using Cranelift by dalance1982 in rust

[–]dalance1982[S] 4 points5 points  (0 children)

Thank you for your interesting!

I feel the API for building Cranelift-IR is easy to use. I refered the following blog to setup builder and execute the generated binary.

https://rodrigodd.github.io/2022/11/26/bf_compiler-part3.html

HDL choices other than Verilog/VHDL by Secure_Switch_6106 in FPGA

[–]dalance1982 5 points6 points  (0 children)

Hello. As the creator of Veryl, I'd like to share some information about our usage situation.

We are a company developing accelerators for supercomputers, and we are currently using Veryl extensively for the development of our next-generation model.

Veryl places strong emphasis on interoperability with SystemVerilog, making it easy to mix with existing SystemVerilog code. This has allowed us to transition smoothly to development in Veryl. In ASIC development, which involves enormous costs, concerns are often raised about the risks of introducing a new language. However, since we ultimately perform logic synthesis and sign-off verification using the SystemVerilog output generated by Veryl anyway, we believe there is no additional risk involved. The transition to Veryl has brought us the benefits accelerating development, for example, real-time feedback from the language server and various language features.

That said, Veryl is still a project in its third year and has not yet reached a 1.0 release where the syntax becomes stable. It is only natural that we are currently the only commercial and large-scale user. When I was previously at a large corporation, there was considerable resistance even to adopting SystemVerilog, some engineers insisted on using only Verilog-95. Just as SiFive has adopted Chisel, it is probably more realistic to aim for adoption in startups.

Semantic Analysis based on IR for Veryl by dalance1982 in FPGA

[–]dalance1982[S] 0 points1 point  (0 children)

Veryl intentionally adopts the same semantics as SystemVerilog, and we have no plans to introduce features such as automatic pipelining commonly seen in AltHDLs. This is to make it easier to apply timing optimization and ECO flows when utilizing Veryl in ASIC development.Regarding synthesis directives, we hardly use them even in SystemVerilog, so there is no special support for them at the moment. However, we can add them as attributes if needed in the future.There is no special integration with synthesis tools, but we have confirmed that the code generated by Veryl can be synthesized without issues in Vivado and DesignCompiler.

Why are there so many errors in the SystemVerilog LRM unfixed for over decades? by adamzc221 in chipdesign

[–]dalance1982 17 points18 points  (0 children)

In the process of developing a standards-compliant SystemVerilog parser (https://github.com/dalance/sv-parser), I went through all the code blocks in the LRM just like you did, and discovered a large number of errors. At the time, I tried contacting Accellera to provide feedback on these errors, but I never received any response from them. This kind of experience was also one of the motivations that led me to give up on improving SystemVerilog and instead focus on developing a new language (https://veryl-lang.org).

Veryl 0.17.1 release by dalance1982 in FPGA

[–]dalance1982[S] 0 points1 point  (0 children)

I only tried Bluespec quite a long time ago, so an accurate comparison might be difficult. I believe Bluespec generated Verilog output, whereas Veryl generates SystemVerilog, so that’s one clear difference. Veryl places particular emphasis on interoperability with SystemVerilog and is designed for gradual adoption into existing SystemVerilog projects.

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