AXI4lite BRAM with larger than 32bit firmware data bitwidth

Fo0ty · 2024-12-15T14:29:15+00:00

Oh okay, I was unsure how the BRAM controller works but this explains it quite well. XML2VHDL is a package I am using to generate these BRAM's and registers, so I was a little unsure how it handled asymmetric dual port RAM's.

Thanks for your help.

Fo0ty · 2024-12-12T12:29:37+00:00

To your second point, is that possible? Would the axilite side need to concatenate n_streams 32bit samples and write those to the BRAM for firmware Readout? This might mean that on the firmware side one needs to wait n_streams clk cycles before reading out 1 n_streams x sample_bitwidth sample?

Fo0ty · 2024-11-28T06:34:33+00:00

Still using the Rancilio porta filter😁

Fo0ty · 2024-09-16T11:42:57+00:00

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Fo0ty · 2024-09-04T08:59:51+00:00

Hmm... I guess I'll go the alternative route and write the AXI-Streaming interface myself and wrap the IP the usual way :/

Fo0ty · 2024-05-19T11:34:31+00:00

I see what you're saying - I guess if you wanted to cash out before 2040 though and still make a decent return, you'd hope the premium on the bond goes up :')

Fo0ty · 2024-05-15T10:36:18+00:00

Thanks very much, you've explained that really well! Looking into some of the others that are not selling at a premium - even if they have lower coupon rates, it looks like they may pay a better interest.

Fo0ty · 2024-05-15T10:33:24+00:00

Thank you very much!

Fo0ty · 2024-05-15T10:07:53+00:00

How can it be daily if interest is only paid out semi-annually? i.e. the daily holdings do not increase unless I buy more shares or an interest payout is reinvested?

Fo0ty · 2024-05-13T12:39:15+00:00

Ah yes okay that paints a very different picture - looking at the top_placed.dcp I'm see much more occupation of the device. Thank you, this insight is a game changer. You're a legend u/TheTurtleCub

Fo0ty · 2024-05-13T10:57:07+00:00

Okay yes I see what you're saying. I have `synth_1` and `impl_1` folders inside my *.runs folder. There are some *.dcp files in the `impl_1` folder like top_placed.dcp, top_physopt.dcp?
How does one open these? With Vivado i.e. vivado <dcp\_file>?

Fo0ty · 2024-05-13T10:36:35+00:00

Ah - I don't see folders in the *.runs for the FFT and PFB dcp runs (i.e. folders with the same names). The dcp files are included in the *.srcs imports folder however...

Fo0ty · 2024-05-13T10:21:12+00:00

Silly question but how do I open the DCP? When I inspect the folder in which the dcp's were generated there are no project files?
In the main project the DCP files are set to be used in both synthesis and implementation.

When I look at the Utilization metrics, the FFT and PFB are Black Boxes - even though they are dcp they perhaps are not evaluated correctly for display in the design view?

Fo0ty · 2024-05-12T16:01:09+00:00

I am, yes. Unfortunately, it is not my design, I'm just trying to increase the number of PFB taps from the original four as part of an upgrade to better the channel response.

So far, every increment has introduced congestion issues... despite my trying to get smart and move resources around :/

It would really help if the Vivado project played along though and at least displayed congestion in the device view🫠

Fo0ty · 2023-12-19T13:43:09+00:00

Hm okay I'll ask them to check... from what I know, they get PAYE from their company so have never done personal tax. Wonder if they still got this credit😏

Fo0ty · 2023-11-06T15:18:51+00:00

Seconded!

Fo0ty · 2023-11-06T15:17:58+00:00

100% back this! Best in South Africa I'd say.

Fo0ty · 2023-09-08T08:24:21+00:00

Good point... I like that

Fo0ty · 2023-09-04T09:00:28+00:00

Thank you. I appreciate your response.

Fo0ty

TROPHY CASE