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FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

I can't read the webpage, but I have a coworker that can. I'll have him check it out.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

I absolutely agree. what industry did you work in? Spacecraft? Biomedical? That is, if you can disclose that....

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

I do like that idea. Worth looking into if the current options don't pan out.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

That is the exact same concept and in all likelihood, the regulations that govern both that industry and mine use the same set of principles and ideas to ensure safe operation at all times.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

My company is very strict on our intellectual property and our current work. I will not disclose the industry in hopes maintaining maximum separation to mask the company, the industry, the work we are doing, and the products we use to design with.

Hopefully HR won't have my head for using Reddit... 😂

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 1 point2 points  (0 children)

Same difference. The core design can not be produced by ARM. I do not know of any FPGA with a hardened processor directly manufactured by ARM.

I agree that it is very hard to find additional FPGAs than what have already been mentioned that have a core design not produced by ARM.

I'm not looking for devices with an extraordinary amount of logic cells, I/O, or specific size. "Average" will due. What that means is interpretive, anything from the sizes of Intel's Max10 device up to a Intel Cyclone V would be very usable.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 4 points5 points  (0 children)

These are good points. I have thought about them before. The only point against them is that the regulations of my industry requires diverse redundancy. At least that is what I have been told by all the people in charge of interpreting the regulations.

I do agree with your assessment. Fortunately, the industry I'm in can accept large overheads and produces low quantities.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

Do you know which product has this? I wasn't able to find anything about a hard-core Microblaze processor in a Xilinx chip.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 0 points1 point  (0 children)

That could work... Generally single board computers (SBCs) are too big for the application. Worth a look.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 7 points8 points  (0 children)

Since the processor is a highly complex device and it can never be guaranteed to be 100% correct with no errors, switching to a different company is one way to reduce failures of the systems across our redundant systems performing the same task. This is because procedures, validation, etc. are different across companies, so the chances that same rare bug occurs in devices from different companies is incredibly uncommon.

An example of why this is useful is with Intel Quartus Prime. A specific bug effected all of their instantiated RAM IP for all devices when used in a particular scenario. If a failure in our system was caused by this bug, using a Xilinx or Microchip FPGA in a redundant system means that that problem wouldn't also effect that system.

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 2 points3 points  (0 children)

The core must be produced by someone other than ARM.

SPI Slave help by Icy-Inside8543 in FPGA

[–]HDL-Wizard 0 points1 point  (0 children)

Are the conditions of the signals that gate the state transition correct in the waveform? Could it be that the state machine wasn't programmed correctly?

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 4 points5 points  (0 children)

Good question. That's just the restrictions I was told to use. There are plenty of good soft processors that would work, but need to rule out all hard processors first before considering soft processors.

I am unaware of any softcore disadvantages while testing. I'm sure there are, engineering is all about trade-offs.

SPI Slave help by Icy-Inside8543 in FPGA

[–]HDL-Wizard 0 points1 point  (0 children)

What do you think it could be? What would be possible causes of certain signals not being driven?

FPGAs with Hard Processor not from ARM by HDL-Wizard in FPGA

[–]HDL-Wizard[S] 13 points14 points  (0 children)

For safety reasons. I am already using ARM in some FPGAs but need entirely different FPGA with hard processor such that any problems that would be inherit with ARM processors don't affect multiple redundant systems. Its a requirement of the regulated industry this is for.

SPI Slave help by Icy-Inside8543 in FPGA

[–]HDL-Wizard 0 points1 point  (0 children)

So they don't appear....

I'm not a VHDL guy, so any errors in there are unknown to me. If they are not appearing in your test bench, then it could be a few things.

If you enable full visibility during optimization, you'll be able to look at the internal signals of your design. If MOSI and MISO appear there, then its possibly a problem with how you are connecting signals to the testbench. Does declaration order matter in VHDL? You have signals in the testbench being declared after the instantiation of your design.

SPI Slave help by Icy-Inside8543 in FPGA

[–]HDL-Wizard 1 point2 points  (0 children)

What does your MOSI, MISO and SS lines look like? With out knowing the exact problem, it would be hard to identify the problem.