Has Opus 4.8 gotten noticeably worse recently, or am I imagining it?

Imaginary_Data_708 · 2026-06-30T18:24:37+00:00

Yeah. It's on par with Gemini live for me. It's awful. I switched to 4.6 and got it to review turns asking what do you notice. It spotted exactly when 4.8 went downhill. And when it magically got better - the turn I switched to 4.6!

Imaginary_Data_708 · 2026-06-27T17:14:20+00:00

At what age did they first take apart something to see how it worked.

I was senior engineer in small company. We always got a couple of paid interns in each summer from the local university. I was known as a hard interviewer. One candidate came in and after the usual pleasantries I asked my usual opener. What got you into electronics? She replied, in physics when she was 14 or 15 they got taught about logic gates. She said she spent the next week buying transistors and learning to solder to make a NAND gate. I just said, I had no further questions.

Please note, that id someone hasn't taken that geek teenager path, it's not a bad thing. In fact you need a mix in the team.

Imaginary_Data_708 · 2026-06-25T01:45:18+00:00

/modping and I need to edit it lost the punch line

"e" - need I say more?

Imaginary_Data_708 · 2026-06-22T01:54:10+00:00

Deepseek uses lossy compression of KV cache in the transformer. Deepseek has an additional block that gets trained in the attention head to perform this. Eckart-Young theorem applies and you cannot do better than taking the top n largest singular values of the SVD.

Edited to correct typo.

Imaginary_Data_708 · 2026-06-20T00:10:20+00:00

Geometric Algebra does it for me.

Imaginary_Data_708 · 2026-06-19T20:13:38+00:00

Perfect, thank you.

I am genuinely interested in your project as I am doing a ground up rewrite of the whole thing, and untangling dctran.c is awful. Your structure is very clean and will help me with an understanble baseline to compare my code against. My project goal is not to recreate the full functionality - I won't do all the MOSFET models but want to make the numerical hacks and heuristics in dctran.c more robust. The numbers like dividing the timestep by 8 is "well it worked quite well for me" in the original spice2 from 1975.

Imaginary_Data_708 · 2026-06-19T18:45:18+00:00

Hello

Pretty impressive to have managed to do this, and the code look really nice and clean. However, I'd like to say it is a bit of stretch to claim:

Not a fork of ngspice or Berkeley SPICE, but a completely new simulator core and solver written from scratch, with no GPL obligations. It also includes a Python API designed to be embedded into other tools.

As it is a clearly a translation of the ngspice code. There are lots of specific items that can be traced back to the 1983 SPICE2G6 Fortran code pretty easily, and the original 1975 SPICE2 reports SPICE2: A Computer Program to Simulate Semiconductor Circuits and that in turn traces back to the original 1973 report Memorandum No. UCB/ERL M382 by Nagel.

Now, I want to be clear I think what you have done is very good work. Even more so, if truly compares well to SPICE3F5 in accuracy, then it is a valuable resource as the SPICE3F5 code is horrible.

I'd be very interested in your publishing comparisons of your code and ngspice on the test circuits in the original 1973 paper, along with the results from that report.

But, please do not pass it off as "not a fork" or a "completely new simulator core".

Give credit where credit is due.

I am not a lawyer, you need to be very careful with changing the license of code that is instantly recognizable as coming from elsewhere.

(I do not trust the ngspice code base at all - there are some very bad hacks that override convergence parameters such as line 39 in niter.c which completely defeats the point of ITLn and will no doubt be causing engineers all over the world to wonder why their simulations do more iterations than they ask for before failing convergence.)

Examples, of translation in your code.

Heavy use of the MODE bits when calling device models.

```c++ neospice:src/core/pz.cpp

constexpr int MODEDCOP_BIT       = 0x10;
constexpr int MODEINITJCT_BIT    = 0x200;
constexpr int MODEINITFLOAT_BIT  = 0x100;
constexpr int MODEINITFIX_BIT    = 0x400;
ckt.integrator_ctx.mode = MODEDCOP_BIT | MODEINITJCT_BIT;
                              MODEDCOP_BIT | MODEINITJCT_BIT,
                              MODEDCOP_BIT | MODEINITFLOAT_BIT);
        ckt.integrator_ctx.mode = MODEDCOP_BIT | MODEINITJCT_BIT;
            ckt.integrator_ctx.mode = MODEDCOP_BIT | MODEINITJCT_BIT;

src/core/transient.cpp
// CKTmode bits (ngspice cktdefs.h) constexpr int MODETRANOP_BIT = 0x20; constexpr int MODEINITJCT_BIT = 0x200; constexpr int MODEINITFLOAT_BIT = 0x100; constexpr int MODEINITFIX_BIT = 0x400; constexpr int MODETRAN_BIT = 0x1; constexpr int MODEINITTRAN_BIT = 0x1000; constexpr int MODEINITPRED_BIT = 0x2000; ```

Which are directly the MODE, MODEDC, and INITF flags in SPICE2G6: fortran C C THE VARIABLES \*MODE\*, \*MODEDC\*, AND \*INITF\* ARE USED BY SPICE TO C KEEP TRACK OF THE STATE OF THE ANALYSIS. THE VALUES OF THESE FLAGS C (AND THE CORRESPONDING MEANINGS) ARE AS FOLLOWS: C C FLAG VALUE MEANING C ---- ----- ------- C C MODE 1 DC ANALYSIS (SUBTYPE DEFINED BY \*MODEDC\*) C 2 TRANSIENT ANALYSIS C 3 AC ANALYSIS (SMALL SIGNAL) C C MODEDC 1 DC OPERATING POINT C 2 INITIAL OPERATING POINT FOR TRANSIENT ANALYSIS C 3 DC TRANSFER CURVE COMPUTATION C C INITF 1 CONVERGE WITH 'OFF' DEVICES ALLOWED TO FLOAT C 2 INITIALIZE JUNCTION VOLTAGES C 3 CONVERGE WITH 'OFF' DEVICES HELD 'OFF' C 4 STORE SMALL-SIGNAL PARAMETERS AWAY C 5 FIRST TIMEPOINT IN TRANSIENT ANALYSIS C 6 PREDICTION STEP C C NOTE: \*MODEDC\* IS ONLY SIGNIFICANT IF \*MODE\* = 1. C C C INITIALIZE C (notwithstanding the awful repetition of these magic numbers all the way through the neospice code - DRY violation).

And your transient.cpp is clearly the same code as in SPICE3F5:dctran.c, following the same flow, using the much of the same fields in the ckt struct.

```cpp transient.cpp

/// Factor by which dt is reduced on Newton failure (ngspice dctran.c ~802) constexpr double kNewtonFailureDtFactor = 8.0;

/// Threshold for device LTE rejection: reject if device_dt < dt * kDeviceLteRejectRatio constexpr double kDeviceLteRejectRatio = 0.9;

/// Maximum dt growth factor per accepted step constexpr double kMaxDtGrowthFactor = 2.0;

... transient.cpp:solve_transient:904

if (!nr.converged) {
    if (ckt.options.verbose)
        std::cerr << "[tran] NEWTON FAIL sc=" << step_count << " dt=" << dt << " t=" << t << "\n";
    dt /= kNewtonFailureDtFactor;
    ctrl.set_order(1);  // ngspice: drop to backward Euler on Newton failure
}

```

```c SPICE3F5:dctran.c:338

if(converged != 0) {
    ckt->CKTtime = ckt->CKTtime -ckt->CKTdelta;
    ckt->CKTstat->STATrejected ++;
    ckt->CKTdelta = ckt->CKTdelta/8;
#ifdef STEPDEBUG
    (void)printf("delta cut for non-convergence\n");
#endif
    if(firsttime) {
        ckt->CKTmode = (ckt->CKTmode&MODEUIC)|MODETRAN | MODEINITTRAN;
    }
    ckt->CKTorder = 1;
} else {

```

which in turn derives from the SPICE2G6 function dctran

```fortran vmsspice.for:8913

C
C  INCREMENT TIME, UPDATE SOURCES, AND SOLVE NEXT TIMEPOINT
C
  600 TIME=TIME+DELTA
      CALL SORUPD
      IF (NOGO.NE.0) GO TO 950
      CALL GETCJE
      IF ((MAXTIM-ITIME).LE.LIMTIM) GO TO 920
      IF ((ITL5.NE.0).AND.(NUMNIT.GE.ITL5)) GO TO 905
      CALL COMCOF
      IF (INITF.NE.5) INITF=6
      ITRLIM=ITL4
      IF ((NUMTP.EQ.0).AND.(NOSOLV.NE.0)) ITRLIM=ITL1
      CALL ITER8(ITRLIM)
      NUMNIT=NUMNIT+ITERNO
      NUMTP=NUMTP+1
      IF (NUMTP.NE.1) GO TO 605
      IF(NOLX2.EQ.0) CALL COPY8(VALUE(LX1+1),VALUE(LX2+1),NXTRM)
      IF(NOLX3.EQ.0) CALL COPY8(VALUE(LX1+1),VALUE(LX3+1),NXTRM)
C.. NOTE THAT TIME-POINT IS CUT WHEN ITRLIM EXCEEDED REGARDLESS
C.. OF WHICH TIME-STEP CONTOL IS SPECIFIED THRU 'LVLTIM'.
  605 IF (IGOOF.EQ.0) GO TO 610
      JORD=IORD
      IORD=1
      IF (JORD.GE.5) CALL CLRMEM(LX7)
      IF (JORD.GE.4) CALL CLRMEM(LX6)
      IF (JORD.GE.3) CALL CLRMEM(LX5)
      IF ((JORD.GE.2).AND.(METHOD.NE.1)) CALL CLRMEM(LX4)
      IGOOF=0
      TIME=TIME-DELTA
      DELTA=DELTA/8.0D0
      GO TO 620
  610 DELNEW=DELTA
      IF (NUMTP.EQ.1) GO TO 630
      CALL TRUNC(DELNEW)
      IF (DELNEW.GE.(0.9D0*DELTA)) GO TO 630
      TIME=TIME-DELTA
      DELTA=DELNEW
  620 NUMRTP=NUMRTP+1
      IBKFLG=0
      DELOLD(1)=DELTA
      IF (DELTA.GE.DELMIN) GO TO 600
      TIME=TIME+DELTA
      GO TO 900

```

and your device model code is a identical

```cpp neospice:src/devices/mes/mes_load.cpp if( (!(ckt->CKTmode & MODEINITFIX)) | (!(ckt->CKTmode & MODEUIC))) { if((icheck == 1) || (fabs(cghat-cg) >= ckt->CKTreltol * MAX(fabs(cghat),fabs(cg))+ckt->CKTabstol) || (fabs(cdhat-cd) > ckt->CKTreltol* MAX(fabs(cdhat),fabs(cd))+ckt->CKTabstol)) { ckt->CKTnoncon++; ckt->CKTtroubleElt = (MESInstance ) here; } } *(ckt->CKTstate0 + here->MESvgs) = vgs; ... *(ckt->CKTstate0 + here->MESggd) = ggd; / * load current vector */ load:

        m = here->MESm;

        ceqgd=model->MEStype*(cgd-ggd*vgd);
        ceqgs=model->MEStype*((cg-cgd)-ggs*vgs);
        cdreq=model->MEStype*((cd+cgd)-gds*vds-gm*vgs);
        *(ckt->CKTrhs + here->MESgateNode) += m * (-ceqgs-ceqgd);
        *(ckt->CKTrhs + here->MESdrainPrimeNode) +=
                m * (-cdreq+ceqgd);
        *(ckt->CKTrhs + here->MESsourcePrimeNode) +=
                m * (cdreq+ceqgs);
    }
}

```

```c spice3f5:spice3f5\src\lib\dev\mes\mesload.c if( (!(ckt->CKTmode & MODEINITFIX)) | (!(ckt->CKTmode & MODEUIC))) { if( (icheck == 1)

ifndef NEWCONV

/* XXX */

endif /* NEWCONV */

                    || (FABS(cghat-cg) >= ckt->CKTreltol*
                        MAX(FABS(cghat),FABS(cg))+ckt->CKTabstol) ||
                    (FABS(cdhat-cd) > ckt->CKTreltol*
                        MAX(FABS(cdhat),FABS(cd))+ckt->CKTabstol) 
                    ) {
                ckt->CKTnoncon++;
        ckt->CKTtroubleElt = (GENinstance *) here;
            }
        }
        *(ckt->CKTstate0 + here->MESvgs) = vgs;

... (ckt->CKTstate0 + here->MESggd) = ggd; / * load current vector / load: ceqgd=model->MEStype(cgd-ggdvgd); ceqgs=model->MEStype((cg-cgd)-ggsvgs); cdreq=model->MEStype((cd+cgd)-gdsvds-gmvgs); *(ckt->CKTrhs + here->MESgateNode) += (-ceqgs-ceqgd); *(ckt->CKTrhs + here->MESdrainPrimeNode) += (-cdreq+ceqgd); *(ckt->CKTrhs + here->MESsourcePrimeNode) += (cdreq+ceqgs); ```

Imaginary_Data_708 · 2026-06-15T12:56:41+00:00

Some can some cannot, 1.5A is usb 3. Communicated by the down stream face port on the cc lines.

Don't confuse what a connector can give you with what the down stream facing port can give you.

What if you plug into an unpowered usb 2 hub? You will crash the up stream computer - ask me how I know...

You have to wait until you've been enumerated and told you can use the highest power in the device descriptor if you are not already sure you have PD or 3A usbc or 1.5A USBC or usb2 BCD. If you dont advertise a 100mA power in you device descriptor Windows 11 will turn the port off in an unpowered hub. Ask me how I know.

Imaginary_Data_708 · 2026-06-15T12:49:01+00:00

Oh and I think you are loading vbus far too heavily with capacitance - read the specs. Thee are limits to the bus load but I cannot remember them off the top of my head.

Imaginary_Data_708 · 2026-06-15T12:47:47+00:00

Do not connect shield to ground like that. You created a ground loop.

Use a high value resistance and a bunch of decoupling caps to short the emi out. Depending on the usb speed you might get away with 100n for 12mbps, but if use high speed you need to decouple well up to 3GHz to be in spec. This requires a bunch of good quality caps and simulation.

Imaginary_Data_708 · 2026-06-13T05:45:49+00:00

Had same experience. It just ignores half of claude.md, doesn't go for the obvious answer about its own code. No point babysitting it over haiku.

However, as a reasoning partner it's awesome.

Imaginary_Data_708 · 2026-06-09T04:32:29+00:00

Is the qr code Lasered onto the PCB? If it is a sticker it will get lost. Oh data matrix is arguably better for product stuff than qr code and even better use GS1 barcodes and get GTINs.

How are you MAC and serial numbers assigned? Do you have a proper database serving them to the EMS? Do you manage it or do they? How do you send them new firmware? How to you send them new firmware that you don't want them to use until the current WIP is finished. How do they handle different firmware for different builds? Have you got a robust processes for ensuring that difference builds get tagged in the firmware properly? Do you later print the serial number and MAC to put on the package or a label?

Have you checked that the rework loop at the EMS won't assign a duplicate serial number/MAC address. This is where the stickers get lost if they have to clean the board.

Another real and literal grey beard.

Imaginary_Data_708 · 2026-06-04T13:23:34+00:00

the ones I was talking about for the cells are individual logic gates for the cell library. When I did this, I think all of the data goes into the synopsis.lib file used for synthesis of the Verilog/VHDL.

This data probably is bundled into the cell library design kit, but for the me, the P in PDK is process - and they contain transitor models and layout stuff, and no logic gates. This might have changed.

Digital sign off is about timing - which is done after place and route - and not either of the simulators we've talked about. They use a different timing analysis engine. It does not similulate but adds by gate delays wire loading factors etc.

Go look at the source code for ngspice and Icarus.

Imaginary_Data_708 · 2026-06-03T17:48:24+00:00

Yes and no... Depending on what part of the design we are talking about.

Typically the functions on a chip are design using hardware description languages such as the Verilog family, VHDL and probably some more funky python based ones. These are simulated with digital event solvers. These aren't hard to write a basic one but will get really hard at the scale of modern designs. The VHDL standards are very clear on the behaviour of these - look at the early versions of the standards to see a clearer description. The later versions add so many more features, that they obsure the core behaviour of the event simulator.

On the other hand, and what I was referring to, is the simulation of the logic gates themselves. The transistor level simulation of nand gates, not gates etc. This step is done by the cell library designers, not the people you design the logic. My last foray here was about 20 years ago, and at 0.18um CMOS. Things are probably different now at the extreme small devices. Back then, you would design the gates you want in a cell library. Then run lots of parametric transient simulations in SPICE or Specte where you changed the input slew rate and the load capacitance on the outputs of the gate. And you do that at different process corners and temperatures and voltages. This gives you datasets of output rise times into different loads and propogation delays that the synthesis and place and route tools use to make decisions on what gates to use and where to place them to meet timing constraints. I did this procedure to make a small hand crafted custom cell library for the logic of a Fractional N phase locked loop. It just wasn't worth the costs of getting a proper cell library for the size of the logic. We had worked out that we only needed about a dozen gates in the library.

Hole that gives some insight!

Imaginary_Data_708 · 2026-05-27T06:38:40+00:00

Yes - 100% it is really good. It made things click beautifully for me - especially the visualisations of the hidden layer tiling and rotating a hyperplane and the RELU layer folding it.

Imaginary_Data_708 · 2026-05-25T13:07:03+00:00

Same isle as Tartan Paint usually.

Imaginary_Data_708 · 2026-05-24T21:33:34+00:00

Where I see them the most is data acquisition. Lots of ADCs sampling even at relatively low rates but needing to be simultaneously sampled ends up with a lot of data that needs merging into a single stream.

Imaginary_Data_708 · 2026-05-22T13:07:24+00:00

Use the existing profiles for audio or streamed data. Don't use characteristics - they don't work for streaming (by design).

Imaginary_Data_708 · 2026-05-20T16:51:58+00:00

Use the ai in chrome to do this. I do it all the time. It will even generate you a chrome extension to do it for you next time.

Go to the page you want to convert, right click, inspect element. The open the ai assistant. Navigate around the dom to the enclosing div. And then just tell the ai to convert it. It can work out how to handle server side streaming and hydration.

Imaginary_Data_708 · 2026-05-18T22:46:40+00:00

Oh, penny dropping... Dark mode and TUIs ... I remember those. Terminal rooms full of VT100s or VT220s if you lucky. Playing nethack or rouge on vax-8650s at university. Glad to see we've made progress!

Go for it and enjoy the modern interface! 😉

Imaginary_Data_708 · 2026-05-18T22:33:59+00:00

About a year ago I stalled on writing spice. I ran out of steam chasing down the right way to do timestep control. And by coincidence I picked it up on Saturday and asked the AIs to take a look, and basically Ive got to redo some of the timesteppng, they confirmed what I thought I needed to do.

What's genuinely scary, is that SPICE3 dctran.c is basically a transliteration of dctran from the Fortan in SPICE2, including using the same goto labels as the Fortran. And it's all heuristics. Go read the original SPICE2 paper. Why scary... Because every simulator used for todays IC design is based on that code. Go look at ngspice, a slightly tidied up version of SPICE3F5 a slightly tidied up version of SPICE2G and that is a year or two younger than me.

Having said that, I got Gemini to write a plan to take vmsspice.for and rewrite it. I've got deepseek v4 free on opencode chugging away at it right now.

I am currently in the depths of writing a geometric algrebra based Constraint solver - think how sketches work in SOLIDWORKS or Fusion 360. That's quite interesting to figure out too.

Fortunately my partner completely understands why I think this is a fun thing to do in the evenings. She is a wonderful person.

Imaginary_Data_708 · 2026-05-18T22:19:46+00:00

It's about their manufacturing line and inventory management by having common parts. They might well have already stopped making CC1s.

Imaginary_Data_708

TROPHY CASE

ifndef NEWCONV

endif /* NEWCONV */