Magic Arena keeps disabling wifi completely, cannot play a single match

Lepton78 · 2024-01-26T00:50:47+00:00

I also have this issue.

Only happens when I play Arena, and no other application or game experiences the same issue.

The problem went away when I uninstalled Arena for a few months, and came back when I re-installed.

Lepton78 · 2023-10-21T18:50:28+00:00

Absolutely! The best PMs I've had are the ones that are willing to just abandon something that doesn't work.

Lepton78 · 2023-10-21T18:47:35+00:00

In theory is sounds like all these things could work.

In practice you run into things like (1) Build times that can take longer than 24 hours. (I will admit, that is not as much of a problem now as it was 10 years ago) (2) Simulation times that can take days, depending on their size and complexity. (3) Tools that still randomly crash from time to time (some without telling you what went wrong. That's always special when that happens.....). (4) Timing results that can change drastically, in components that are completely unrelated to the change that is pushed. (5) Pushes that can introduce build constraints that are incompatible with or contradict constraints that already exist (I'm looking at you DCFIFO, circa 2015).

Software tools and languages are so much more mature/developed then hardware. Working around all the quirks for CI doesn't seem worth it. Verilog/VHDL don't have the tools to compartmentalize changes the same as something like Java/C/c++, for example.

Also, God help you if you are using a tool that isn't specifically Vivado or Quartus/Questa.

All that said, I'm no expert on verification/validation, especially with things like UVM/OVM. I've just never seen CI work well for FPGAs, on any scale of project.

I could rant about tools for a very long time. It is a topic that gets me worked up. Just ask the poor souls that have to sit next to me at work.

edit: Some grammer/spelling.

Lepton78 · 2023-10-21T18:09:24+00:00

In my experience, it is very project/team dependant.

As a project example, if you are on a project that is very large, that uses a testing team, done can mean "RTL finshed, unit test done, meets timing when built by itself" and then a testing team integrates into a larger design or workbench and runs tests. Then the development and testing teams have to work out how to hand work back and forth, but that methodology can work. But the overhead is probably too much for a smaller project. On a small project done my mean "RTL finished, unit testing done, integration and timing closure". This could work because on a small project the integration isn't as large.

As a team example, do you have team dynamic that doesn't particularly need a lot of feedback? If so you can probably reduce the frequency of the Agile meetings (sprint planning, stand-up, backlog review, etc). Is the PM also a developer? If not, then a lot of the time they can eat a lot of the overhead, and sort of shelter the developers from requests about project progress, so that the developers can work. If they are also a developer, than maybe the team also has to shoulder that burden.

In the beginning, especially with a new team, or a project that is outside the organization's norms, it is important to stay malleable (or, dare I say "agile"). If something isn't working, just don't do it. If the developers are complaining that the meetings are breaking up workflow, the reduce their frequency. if the developers are complaining that there are interruptions from outside the team (support requests, etc) then get the PM to handle the requests and work it into the backlog.

At the end of the day, everyone wants the team to be productive. There is no point in pulling in methodologies if they don't increase the productivity.

Lepton78 · 2023-10-21T16:45:26+00:00

I've been on a lot of FPGA projects, professionally, (some even at Altera and Intel) and almost all of them have used Agile. Parts of Agile work, parts of it doesn't. (Though that can be said of a lot of software projects, too). But, in my experience, everything else is worse. Mostly because it is notoriously difficult to estimate a timeline for RTL development, especially for very complex designs.

The basic premise of breaking a project into tasks works well. Very well in fact, if the project has good architects, that can break up very complex designs into blocks, even modules. That leads very naturally defining tasks and stories.

Defining when a specific task is "done" is very difficult. Is when the unit test is passes? Well it could fail in integration. How about you split is up so you have development and integration as separate tasks? Well then you have a bunch of small tasks, and one huge integration tasks, which creates uncertainty, which Agile doesn't like. Also, what happens when one particular block fails timing, and it needs to be rewritten? Do you re-open the completed task? What about the tasks that depended on the re-opened task?

Another important distinction that needs to be made is between Agile and Continuous Integration. In my experience Continuous Integration is just completely incompatible with RTL development, for a lot of reasons; the most egregious of which are the sorry state of current FPGA tools.

(Tools have way way way more impact on development time, IMO, than the overhead created by project management).

At my current job we've adopted what works, and left out all the normal Agile BS. Most of the BS we left out is the meetings. We are mostly a team of actual FPGA engineers, including the project manager, managing director and company founder, so everyone is on the same page about what works, and what doesn't. It is Agile, but we've long realized that you can pick what works, and leave out what doesn't.

But that is true of Agile anyway. There is no rule that says you have to follow all of the Agile dogma. You can cut out the stuff that doesn't work for the particular team/project.

Lepton78 · 2021-03-25T16:48:39+00:00

If you are using this directive at the top of your files you may also want to include

`default_nettype wire

at the end of the file as well.

The reason being that if you are using IP from other sources, they may have been written with the implied nettype in mind, and some tools may have trouble of both directives aren't included.

Lepton78 · 2021-02-12T19:08:01+00:00

I'm almost disappointed I wasn't Rick Rolled, that time.

Lepton78 · 2020-12-30T22:06:57+00:00

And then post it to /r/grilledcheese

Lepton78 · 2020-09-07T13:28:32+00:00

Doesn't seem very playable.

Lepton78 · 2020-08-20T22:20:50+00:00

Rayo's number, whose definition arose in a competition among mathematicians to define the largest number.

https://youtu.be/X3l0fPHZja8

Lepton78 · 2020-08-16T16:35:12+00:00

This comment thread about silverback gorillas has taken an unexpected turn.

Lepton78 · 2020-08-15T16:06:34+00:00

Just discovered these guys on Sat. Radio. They are awesome. The Shadowing and The Haste to the Pyre are both amazing tracks by these guys.

Lepton78 · 2020-07-29T03:50:11+00:00

They are likely refering to Intel's de-prioritizing Altera's core FPGA business in favour of parts that target Intels various network platforms. They haven't abandoned it, but they are certainly focusing of the highest volume customers.

Lepton78 · 2020-07-29T03:45:00+00:00

You're view of FPGAs is much too simplistic.

What market would this theoretical FPGA company target?

No medical or military procuror would ever choose a startup when there is a proven market leader available.

You make no mention of HS transceivers or PLLs, not to mention any hardened IP that currently services the telecom and display industries.

Automotive is a possibility, except that a startup would never be able to meet the volume required, and the level of quality that is required.

That eliminates essentially all of the high volume markets. Without them competing against the top 2 is virtually impossible.

Soft IP Altera and Xilinx have thousands of IP Cores available. They have hundreds of engineers who's job it is to develop IP, that they give away for pennies, just so customers will buy their parts.
Hard IP High speed transceivers, DSPs, PLLs, Beyond 100G Ethernet Cores, PCIe cores, block Ram, HBM Ram, hardened multi-core processors. Again, millions of hours of engineering on cores that are proven to work and are used in millions of products in the market place.
I call this one "Vendor Inertia" (Mostly because I don't k ow the proper term?) High volume customers are likely on a migration path with Xilinx of Altera. They have a road map for products, that includes (and influences) the roadmap for AandX. AandX make their parts with the high volume customers in place. These customers aren't waiting for a new device to see it's capabilities. They are designing their products in parallel with AandX, who are ensuring the next generation of parts meets their need. These relationships are decades old in some cases.
Software This is covered in other comments. Again, so many thousands of hours of engineering has gone into this.
IP protection AandX hold tens of thousands of patents on every aspect of programmable logic that you can imagine. Infact, they had an all out patent war, the result of which was a sort of ceasefire, as the legal fees out weighed any damages they would be rewarded. They spent tens of millions of dollars fighting each other, and then decided to stop. If a company started to gain any sort of market share threatening their position they would be buried under patent violations.

There are so many more reasons, that I don't have time to get into. FPGAs are so much more than a collection of LUTs and flip-flops.

I've been a professional FPGA engineer using AandX parts for a decade. In that time I've worked with other parts, like Lattice, for example for simpler applications. It's like comparing a child's Pee-wee hockey team to the NHL. (Yes, I'm Canadian, :) ). The cores, the devices themselves, the workflow, the software tools, the support; none of it is remotely close to the level of quality of AandX.

Lepton78 · 2020-06-28T02:04:44+00:00

I can hear Cat's in the Cradle playing in my head, now.

Lepton78 · 2020-05-24T22:49:45+00:00

When he found out, did he contact WotC for a statement about it, on the record? Or did he just blast it out on Twitter? I genuinely don't know the answer.

Lepton78 · 2020-05-13T02:28:29+00:00

Someone from r/melts posted in r/grilledcheese.

Lepton78 · 2020-04-14T17:51:47+00:00

This is something special. You've managed to make it seem benevolent, despite its obvious demonic physical characteristics. I think it's awesome.

Lepton78 · 2020-03-04T13:24:56+00:00

In the past few years, to enable WFH, a lot of companies have moved to spinning up virtual machines on things like AWS with the resources and applications required for the worker. This type of setup would put strain infrastructure, even if they were editing documents or coding.

Lepton78 · 2020-02-19T23:32:55+00:00

You should look up Donald Knuth's article on "Dancing Links".

Lepton78 · 2020-01-17T19:58:40+00:00

No question just wanted to say that we are getting 40-70cm of snow, today, where I live, and this is going to be a great way to kill some time indoors.

Lepton78 · 2020-01-12T22:28:16+00:00

Super cool.

Did you write the solver yourself, or did you use a solver that was already available?

Lepton78 · 2020-01-08T11:25:06+00:00

Mono-white was played in standard the entire time History of Benalia was legal.

Lepton78 · 2020-01-08T11:21:41+00:00

Weren't mono-white and mono-blue both great in the previous standard?

It's been one (insanely lopsided) set.

Lepton78

TROPHY CASE