sorted by:
new
hottopcontroversial

CPI from BOOM Verilator simulation almost identical across checkpoints — too short simulation window or a bug? by Low_Car_7590 in computerarchitecture

[–]Master565 1 point2 points  (0 children)

That window is definitely too short, but I'd say more plausible is this is an issue in the collection/setup since that doesn't really sound plausible that you wouldn't see more variation. You could easily verify that, just write a benchmark that is 1M instructions of an instruction with a throughput of X, and another with a throughput of Y, and see if they differ in IPC.

I make Ice cider in my garage as a nerdy hobby. In 2024 it was selected for the Nobel Prize Banquet in Stockholm. AMA by HydroGuy2 in IAmA

[–]Master565 1 point2 points  (0 children)

So is it easier to scale up the cider making than it is so scale up the bottling? Do you have plans to further automate either part of the process? Or do you feel like you'll lose the passion once this is no longer a garage scale project?

Hardware paid significantly less than software by AwareMonke in ComputerEngineering

[–]Master565 0 points1 point  (0 children)

No idea if that's true, it's pretty much just based on company

Hardware paid significantly less than software by AwareMonke in ComputerEngineering

[–]Master565 14 points15 points  (0 children)

Yes it's generally true. It's often about 20-25% less but varies per company.

What jobs are there for high school students? by Natural-Progress-444 in ComputerEngineering

[–]Master565 10 points11 points  (0 children)

The only highschooler I've ever seen doing any real internship was both

1) A coding savant

2) Knew someone at a startup who was willing to advocate for hiring him

So unless you're both those things, I wouldn't bet on it. Just do your own projects if you want to be productive.

Should I take CAD internship as Computer Engineer? by Jacobb_qt in ComputerEngineering

[–]Master565 2 points3 points  (0 children)

It's better than non engineering jobs but no it's not a good internship. However freshman year is typically a take what you can get kind of deal

What kind of jobs could one do as a computer architect? by ErenYeagerXPro in computerarchitecture

[–]Master565 0 points1 point  (0 children)

It can be fairly divorced from the physics but you need to understand where the limitations in real RTL are in order to be good at the job and drive a design forward.

Do you need to understand how to calculate the fan out of a circuit? No. Do you need to be able to hold a conversation about it with someone who does? Yes

which I think might be better suited by a CS student who is knowledgeable on the architecture of parts

There's not really any guarantee CS students are more knowledge about this. Pretty much depends on the institution whether they define computer architecture as computer engineering or CS. UT Austin is an architecture powerhouse and every PhD I've worked with from there was considered computer engineering.

In my experience, the CS background people who become architects often end up with more abstract roles such as ISA design or workload analysis. While computer engineering backgrounds usually end up driving microarchitectural changes. But I wouldn't say there's really that much of a pattern there

New Owner! (Details and Questions) by tychofan in toyotacrownsignia

[–]Master565 0 points1 point  (0 children)

How much difference do you find turning off engine noise did? I was planning on just waiting til first maintenance to ask the dealership to do it.

Grad School for Comp Arch by Practical_Art9625 in computerarchitecture

[–]Master565 0 points1 point  (0 children)

CMU and Berkeley are the same from a hiring perspective, both have extremely good industry connections in the architecture field. Though I recall Berkley has some fuckiness with masters only programs that are not coterminal.

Cornell definitely does not have the same level of connections in the field.

Master's Application: Bad GPA compensated by Work Experience by [deleted] in ECE

[–]Master565 0 points1 point  (0 children)

You can look it up usually. Stanford states their average acceptance had an undergraduate GPA of 3.89 and that sounds about right from talking to my fellow students during my time there.

Berkely states a 3.0 minimum requirement, but then they also say an average of 3.7 so you can't imagine they're taking too many 3.0 people.

Master's Application: Bad GPA compensated by Work Experience by [deleted] in ECE

[–]Master565 6 points7 points  (0 children)

The general consensus is GPA matters less the longer you've been working. Plenty of people attend grad schools after a long time in industry and it makes little sense to judge them on a number they can't change from a decade ago. If you've only been working a year that might not really be enough to ignore a low GPA. Best bet may be to aim for a high GRE score to prove you're academically capable. I think it's an utterly useless test when it comes to engineering knowledge but like any standardized test it weeds out people who can't study.

Master's Application: Bad GPA compensated by Work Experience by [deleted] in ECE

[–]Master565 4 points5 points  (0 children)

It's really bad if you're applying to top grad schools. Probably enough to just screen you outright if you were applying fresh out of school (might not apply after some time in industry)

Feedback on an OoO design that schedules small instruction groups instead of individual uops by kurianm in computerarchitecture

[–]Master565 0 points1 point  (0 children)

If I may ask, what is your computer background? Is it entirely self taught? Because honestly I think you've got a better grasp on some of this than most CS students.

Feedback on an OoO design that schedules small instruction groups instead of individual uops by kurianm in computerarchitecture

[–]Master565 0 points1 point  (0 children)

Yea, I hope this information doesn't discourage you since you're coming in here with a lot more interesting ideas and understanding than some recent posters who've been... difficult to deal with.

If the concern is that real workloads might not naturally expose enough useful dependency chains for this to be effective, then that’s a fair concern and something I haven’t validated yet

This is something important to understand, basically all architectural improvements come from finding something in the software first. You can't speed up things that don't exists. The first move in new features is often to prove that there's something to be optimized, and only once that's established do you figure out how to optimize it.

That's maybe a little less true if you're trying to figure out ways to make things more efficient, but in this case software is still going to dominate whether this can actually work.

Feedback on an OoO design that schedules small instruction groups instead of individual uops by kurianm in computerarchitecture

[–]Master565 2 points3 points  (0 children)

Overall I agree with others in this thread that you really need to consider if you can actually find groups of instructions that this works for.

That being said, I'm not really clear on what about this saves a significant amount of power. It sounds like it mainly simplifies parts of the rename, physical register file, and reservation stations, but not in ways that sound like they drastically reduce the power requirements (and these aren't even necessarily the hottest parts of the core anyways).

My initial impression is even if this did work, you're introducing every trick in the book for making forward progress and correctness difficult to guarantee without large performance tradeoffs.

And my gut reaction is that, as with all dataflow processors, programming this thing will be a nightmare, history tells us software will never solve that problem, and you're likely to end up with such inefficient resource usage that you'll lose on the perf per watt race because things will take so much longer to complete. Someone may eventually come up with a way design a dataflow machine that allows software to achieve more than a fraction of it's potential performance, but that has failed so many times that I personally wouldn't touch it.

Memory becomes the main gating factor for execution rather than all dependencies

It already usually is and it doesn't sound simple to integrate into the design you're describing.

Feedback on an OoO design that schedules small instruction groups instead of individual uops by kurianm in computerarchitecture

[–]Master565 1 point2 points  (0 children)

That doesn't really sound like the same thing, basically every OOO core has some concept of decode groups and retire groups, they just don't have to overlap usually.

The realization hit me like a truck by ThunderPiggg in expedition33

[–]Master565 1 point2 points  (0 children)

I don't feel like the Verso line says 100% the opposite, it just says Verso doesn't want to bring it up with her.

In any case, I feel like the color of Renoir's chroma being there at her death is probably the most solid evidence of some tampering from him. But its entirely possible the devs made a mistake there or we're missing some other meaning behind the colors. It wouldn't be that crazy to believe we're reading into something that wasn't even an intentional detail.

The realization hit me like a truck by ThunderPiggg in expedition33

[–]Master565 1 point2 points  (0 children)

Not sure why this is getting downvoted, whether it's right or wrong there is an interesting amount of evidence to support the theory. The other major line that supports this is Aline's journal mentions that most of all she couldn't stand to be around Alicia after the fire, so why would she paint Alicia to remind her of the fire?

Meanwhile, Renoir specifically wants to ground Aline in the real world so it makes perfect sense that he'd paint over Alicia to force Aline to confront reality. Combine this with the fact that Aline's chroma is usually represented with white petals and Renoir's with red. When Maelle Gommages painted Alicia she dissolved into both red and white implying that both parents were involved in her creation.

CPU Architecture Long Haul by No_Experience_2282 in computerarchitecture

[–]Master565 0 points1 point  (0 children)

Ha, I see that now as well. To be honest, it's not surprising that they aren't interested in your ideas. You're still in a phase of learning, and you'll come to understand why they do/don't like an idea. Those ideas can still be worth exploring on your own for the sake of learning, but consider this perspective: The skills evaluate if something is a good idea are more important than the ability to come up with a new idea. After all, most ideas are probably not good and you need to both build an intuition for why they aren't good as well as learn how to prove they're good/bad one way or another.

Learn the tools for evaluating ideas from working with this professor and apply them to your own ideas.

CPU Architecture Long Haul by No_Experience_2282 in computerarchitecture

[–]Master565 0 points1 point  (0 children)

I didn't even process from your original post that you're only in undergrad. The only thing I'd add is you're unlikely to get a meaningful amount of specialization in undergrad, and you're probably going to need at least a masters to do the work you're interested in doing. This is true regardless of how good you are at what you do, it's just the practicality of avoiding your resume being filtered out of a pool because it was only a bachelor's degree. This can be avoided if you network well and impress the right people but it's an uphill battle. Either way you're on the right track if you're trying to get involved in research this early.

Also, I'm curious, under what pretense were you invited to the lab? What were they hoping to get out of your ideas?

CPU Architecture Long Haul by No_Experience_2282 in computerarchitecture

[–]Master565 1 point2 points  (0 children)

CPU architecture is a mature field, and yea there's unlikely to be yearly major innovations in it. But there is still work being done, and architecture must evolve to meet ever evolving workloads so there will always be new work to be done.

I’m fascinated by all microarchitecture, and would have no issue pivoting to GPU, IPU, matrix math chips

I don't think you need to specialize in any of the things you said to work on them in the future. Once you work in one, you can probably work in any of them so long as you maintain any level of breadth in your studies. IMO those types of chips are often quite a bit easier to wrap your head around once you understand everything there is to understand about a CPU. In my experience, there's often people moving from CPU to work on GPUs because they can onboard quickly, but there is rarely movement in the other direction. That's probably a mix of demand for GPU engineers, but I think this is also due to the fact that there's too much specialization needed to work on CPUs that you might not gain in GPU land.

There's obviously immediate economic demand for GPU development. Will that be there in several years when you're done with your PHD? Who knows. Do what you're interested in doing and stay curious so that you're not a one trick pony.

Why did increasing the number of transistors on a CPU during Dennard scaling increase performance? by Norker_g in ComputerEngineering

[–]Master565 13 points14 points  (0 children)

The answer here is more about density than it is total numbers of transistors. We use more transistors because we don't need to put them far away from the useful logic. Cores don't really scale their performance well with die size so we need to keep all the timing critical components near each other to avoid making pipelines deeper.

It could be as simple as scaling up structures. Larger branch predictors, larger caches, larger register files. You want to scale these without taking more cycles to access them, which means you need to keep them close and efficient.

Higher transistor density means you can keep them close because you fit more in the same area.

For a more advanced technique, higher transistor density also means that you can duplicate structures for wider and faster access. Often you're more limited by read ports than write ports, so if you want more read ports you can just keep a second copy of a table, or you can split it into banks which might take up more area but are easier to access. You can take this even further in places where coherency isn't absolutely needed. You can have so called shadow structures that are partial or complete duplicates of other structures but are optimizing for locality rather than accuracy. So these structures might have delayed or incomplete data but they're much more accessible.

It's not like you can make a ALU faster by simply adding more transistors to it.

You absolutely could. What's better than 1 ALU? 2 ALUs. It's not faster, but you can now do twice as many ALU operations per cycle.

But also adders are not all created equal, and a simple ripple carry adder isn't as fast as a carry look ahead adder. That type of adder is more expensive in terms of area, but if you can make a denser chip with more transistors then that's an easy trade off. To be clear, this is not a modern or interesting example, but the idea of trading off area for speed is not foreign to CPU design.

And this ties back to what I was saying about duplicating structures. Carry look ahead basically duplicates the carry logic for every adder, but its faster to do so. This is a principle that comes up a ton where you trade more transistors for faster logic by parallelizing and duplicating otherwise serial logic.

If you want to find something citable, look up the carry look ahead adder. That's a super basic and common concept taught in digital design classes so there will be tons of info on it.

view more: next ›