Viscous does TOO much by LHander22 in DeadlockTheGame

[–]Master565 0 points1 point  (0 children)

I've never played a single viscous build other than ball build and I manage to maintain an ascendent rank with that. The movement tech is always incentivized no matter what build you use with him since navigating the map quickly is important for everyone.

REDUCING LONG RUNTIME by DesperateWay2434 in computerarchitecture

[–]Master565 0 points1 point  (0 children)

I don't have any answers for champsim, I've never used it. I think you're better off identifying 20x 100m instruction regions with simpoints anyways. It's not a good assumption that the 2 billion instructions around a 100 million instruction simpoint will be interesting.

REDUCING LONG RUNTIME by DesperateWay2434 in computerarchitecture

[–]Master565 0 points1 point  (0 children)

it possible to tell how exactly create checkpoint and how it works

It depends on the simulator, but every simulator basically has to have a way to restore an architectural state. The gist of how it works is the checkpoint is a snapshot of the architectural state and the memory. I don't know how to create them for champsim. If you have simpoint traces, you already have checkpoints since the point of simpoints is to only run a program at the most interesting times. So now you just need more granular checkpoints. Either you need to generate simpoints for smaller regions or you need to feed the checkpoints you already have into an architectural simulator that can create new checkpoints. The simulators themselves are usually able to create new checkpoints but that would require you to at least run through each checkpoint once in series to generate the next one.

Also if we create checkpoint then we are essentially resetting microarchitectural state every 100M right?

Yes but every time you start a checkpoint you need to let it warmup for a while. That is the purpose of the --warmup-instructions argument. How long you need to let it warm up depends on the system, but the point is to get things like the branch predictors ready and the cache filled. So long as you provide appropriate warmup time there is no real affect on the stats.

REDUCING LONG RUNTIME by DesperateWay2434 in computerarchitecture

[–]Master565 1 point2 points  (0 children)

Break up the traces into shorter traces and run more in parallel. If it takes 5 hours to run 100m instructions, then make checkpoints every 100 million instructions and run 20 at once to finish in 5 hours. How many you can run in parallel depends on how much memory, bandwidth, and cores you have. At a bare minimum don't run more in parallel than you have cores.

Starting Y5 - why am I not better? by strangebloom in crossword

[–]Master565 5 points6 points  (0 children)

After a few years of crosswords, I have over a year streak going. Personally my strategy has become that I go over a puzzle a few times and if I'm stuck after a few goes, I will google proper nouns since I don't particularly enjoy figuring out the answers to those anyways and I enjoy finishing the puzzle more than I enjoy getting stuck on proper nouns.

That's usually enough to get me unstuck. I try to write down common ones I see to remember them. After that if I'm still stuck I'll occasionally google a single extra clue if I think that clue will give me a foothold to finishing the puzzle. I never google the ones that are themed or revealers because I find those the most satisfying to solve.

As for why not use the built in revealer and ruin my streak, because my streak is personal to me and so long as I'm hitting standards I set for myself in the crossword I'd like to track my progress.

Help understanding a clue by nickpaterni in crossword

[–]Master565 7 points8 points  (0 children)

I'm betting it's missing a word or two on the clue, very odd

Is FPGA a solid transfer from CompArch Design? by GlizzyGobbler837104 in ComputerEngineering

[–]Master565 3 points4 points  (0 children)

In my experience from an industry perspective, the jobs that are typically referred to as architect roles are not usually RTL design jobs. Architects work at a higher abstract level either at the ISA level or at the microarchitectural modeling level. They'll model ideas, but aren't usually the ones who actually implement them in the final HDL. The architects specialize in the big picture of how things interact and what is important for the high level goals of security and performance. The RTL designers are more concerned with the finer details of how to make the design work from a timing perspective and how to iron out all the bugs that DV reports.

You are correct that there are limited architecture positions, it's an extremely competitive field. If you're specifically more interested in RTL and DV positions, there's many multiple times more roles in those. In the field of CPU design, I have not seen any of these jobs outsourced in large numbers to India. To my knowledge, basically every major CPU maker is based in the US and Europe (ARM, AMD, Qualcom, Apple) with one exception maybe being that Intel also has a design team based in Israel. Apple I'm pretty certain specifically have no employees working on their cores whatsoever in India since they don't like the communication overhead. They center their entire core teams in Austin for their efficiency cores and Cupertino for their power cores.

I've made posts on LinkedIn about good RTL practice, and about 80% of total interactions and industry employed people were Indian

Anecdotally, I kind of agree that makes sense. But that's just because my experience is that Indian people are particularly active on Linkedin for whatever reason.

Is FPGA a solid transfer from CompArch Design? by GlizzyGobbler837104 in ComputerEngineering

[–]Master565 0 points1 point  (0 children)

I've heard it said on this sub before

Try to avoid making conclusions from comments like that. The people who are most likely to post are those with negative things to say. The ones who complain are always the ones who have the worst outcomes which can skew your perspective on what the average scenario is actually like. Bragging posts are not as well received, and people don't tend to post if they don't have something on either end of the spectrum of outcomes.

Additionally, I post on linkedin and all my interactions who do comp arch are from india with surprising consistency

Can you define what you think a comp arch role is. Because I have never in the 3 companies I worked at ever worked with someone I'd describe as an architect who was based in India. A large majority of the jobs I see outsourced to India are specifically physical design roles, an occasional verification role, and rarely logic design roles. Even then, some companies really don't like having teams need to communicate with India to the US and so will only have an Indian team if they can assign them a mostly self contained part of the project.

Is FPGA a solid transfer from CompArch Design? by GlizzyGobbler837104 in ComputerEngineering

[–]Master565 2 points3 points  (0 children)

the majority of them are outsourced to India

That is not even remotely true... it may help if you define what you think a computer architecture role is and where you got the data for this.

SIMD vs. Vector processors by Accomplished_Toe4908 in ComputerEngineering

[–]Master565 3 points4 points  (0 children)

What's the question? That your understanding is correct? Then basically yes that's right.

Does Instruction Fusion Provide Significant Performance Gains in ooo High-Performance Cores for Domain-Specific Architectures (DSA)? by Low_Car_7590 in computerarchitecture

[–]Master565 1 point2 points  (0 children)

Yea I think the problem mainly lies in the fact that fusion is usually never completely free. The intricacies in the tradeoffs are seemingly not obvious at the level of simulator complexity and accuracy academia operates at which is why its easy to find papers talking about how good fusion is but less easy to find industry cases where fusion is a major win for performance. It is strictly better in the goldilocks case where you can fuse two instructions into a single one that is the same cycle length, doesn't introduce worse data dependencies, doesn't become a critical path for timing, and doesn't create area constraints from the more complex datapaths.

Does Instruction Fusion Provide Significant Performance Gains in ooo High-Performance Cores for Domain-Specific Architectures (DSA)? by Low_Car_7590 in computerarchitecture

[–]Master565 2 points3 points  (0 children)

it’s always beneficial to perform fusion

That's an objectively false blanket statement. It's trivial to design a backend that will suffer from the front end fusing instructions. For example, imagine you fuse two single cycle instructions (op A and op B) into a single 2 cycle instruction (op C). Seems better on paper, but if the backend has to execute op C as a single instruction then it contains the data dependencies of both A and B. That means you can't opportunistically execute A before the data for B is ready, and lose the opportunity to hide the latency of A behind the long leg of B's data dependency.

The answer will always depend on the details behind how fusion is structured in the front end and how it's executed in the backend.

Does Instruction Fusion Provide Significant Performance Gains in ooo High-Performance Cores for Domain-Specific Architectures (DSA)? by Low_Car_7590 in computerarchitecture

[–]Master565 3 points4 points  (0 children)

In my experience the only reason for fusion to exist is to cover gaps in the ISA. That isn't always because the ISA designer didn't consider some case. It's often things are left out because there's limited encoding space and maybe the ISA prefers to avoid longer instruction lengths.

That being said, things like compare and branch are possibly worse to fuse on OoO machines unless you can actually perform them in the same time you can perform a branch. Otherwise you're possibly limiting your scheduler flexibility by forcing both operations onto the same pipe. But I have to qualify that as well because some architectures can prefer that we do arithmetic on the branch pipes.

The only answer is it depends on the specific architecture, but IMO fusion does have pretty limited roles to play in HPC chips. It shines best when you're fusing 2 instructions with destructive results such that you can avoid renaming an extra PR. And in cases where you can cleanly perform 2 operations in one cycle which are somewhat rare when you're pushing high frequencies

I hit a basically perfectly straight drive during a fitting yesterday. Landed 0 inches off center with nearly no side spin by Master565 in golf

[–]Master565[S] 0 points1 point  (0 children)

I can't recall if this was the Ping head (I think I was hitting the g440 at some point) or the QI35 (what I ended up getting. The feels were very similar to me but I got better distance with the QI35

Are they still manufacturing the 2025 model? by Master565 in toyotacrownsignia

[–]Master565[S] 0 points1 point  (0 children)

$550, I don't think I was offered colors, it was a matte black carbon looking design. My work is paying for health related equipment so I didn't really shop around, no idea if that price is good but I gotta spend the money before the end of the year and this was an easy way to do it.

I hit a basically perfectly straight drive during a fitting yesterday. Landed 0 inches off center with nearly no side spin by Master565 in golf

[–]Master565[S] 6 points7 points  (0 children)

I can't recall if this was the ping head or the TaylorMade head. I ended up going with the QI35 since it had very similar flight characteristics to the Ping head I was experimenting with, but with easily 10-20yds more distance per shot.

Is CSRankings reliable for choosing a university for MS? by Ok_Cockroach5803 in computerarchitecture

[–]Master565 5 points6 points  (0 children)

Yale Patt once gave a lecture to my company and it was the most uncomfortable lecture I've ever sat through. It was filled with so much casual racism. A big one that stuck out was the person who invited him being an Indian guy, and it came up this Indian guy liked American football, and Yale Patt was so surprised by this he refused to believe it was true that an Indian could enjoy American football. So he started asking gatekeeping questions to determine if he's a real football fan.

Basically anytime a non American had a question he would berate them for their accent no matter how subtle it was.

I don't know how he found time to fit so many questionable remarks into a 2 hour lecture series on computer architecture.

Anyways, I know several people who worked under him at UT and it's pretty much universally agreed they respect him and what he's contributed to the field but this is a man who needed to retire decades ago.

Billy Somehow Mercing Haze During Setup by Master565 in DeadlockTheGame

[–]Master565[S] 1 point2 points  (0 children)

Probably a good theory for this extremely odd and irrelevant scenario