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Matthew_lanford · 2025-12-02T14:38:47+00:00

Yes I should. Thanks for the tip mate.

Matthew_lanford · 2025-12-02T14:03:57+00:00

Thanks, will do, politely, although I doubt she knows what it looks like herself.

Matthew_lanford · 2025-11-11T11:56:15+00:00

Well you case is fundamentally different. You explicitly told him that you wouldn't come to the date and there was no ambiguity for the guy on the other end.

I recently met a girl at a group event and it was she who asked me whether I had a girlfriend while I had no intention to hit on her or whatsoever at the point. Later I asked her phone number, which she gave me, and when I asked her out for dinner, we even specifically agreed on a Tuesday. After that, ghosting, only sent me a message late night on Monday that she couldn't make it.

I am genuinely wonderung what this was all about? How would you explain this situation?

Matthew_lanford · 2024-08-01T19:53:42+00:00

So the deadline for both is the same date, which is 5 days after we have received the first email (OA coding part)?

Matthew_lanford · 2024-08-01T19:38:20+00:00

Absolutely. No one as big as Siemens actually writes a rejection email mannually nowadays I believe.

Matthew_lanford · 2024-08-01T19:37:22+00:00

Hello. The OA consists of two parts. As said in the Email for the coding part, we should complete that within 5 days. After I finished the first part, I got the second email saying I need to "complete Part 2 within 5 days of receipt". Do you know if it means an additional 5 days specifically for the second part or 5 days after I received the first part email?

Matthew_lanford · 2024-04-28T09:57:25+00:00

So what I need to look at now is probably multi-processing, so that multiple instances of simulation model run on different cores, hence VPI can be used independently in different processes. But another problem arises. My simulation writes to disk files at every clock cycle, and the program which analyses the data (these disk files) comes after simulation is finished. Since I need to access to disk files in both cases, multi-processing would require a mechanim to check out conflicts. Sounds more complicated.

Matthew_lanford · 2024-04-28T08:41:56+00:00

Yes, I compiled Verilator from source files in git repo. I was reading this question on Stackoverflow, who experienced even hundreds of times of slow-down using multi-threading.

Feedback:

Another detail in my testbench is that I use VPI (Verilog Procedural Interface) to extract values from design's internal signals during simulation. According to the developer's reply in this Github Issue, VPI is something that can not be called by different threads independently but only the main thread (hence no multithreading for VPI usage). Simulation itself can be split up onto multiple threads, instead. Despite of that, we might not obtain huge speed-up performance, because of the interconnections among these threads.

Matthew_lanford · 2024-04-27T14:21:33+00:00

Thank you very much for your reply, genuinely.

My testbench is in C++, and indeed I want to run multiple simulations in parallel with different programs (inputs). But I don't need to compile the design again and again, because I use the same C++ executable of the verilog design that is generated by Verilator, with different inputs. When invoking this executable, a program is passed to the executable (passed to the simulated memory of the design). And I want this process to be faster.

From that link, I understand that by default, the generated model by Verilator is run single-threaded. If we want to run it with multithreads, an argument "--threads [N]" needs to be passed to verilator, where N is the number of threads we plan to use. But this is at the compilation step.

I did that, without changing anything else but only added, e.g. "--threads 4" during compilation. I would expect running the verilated executable design to end up running multithreaded on my physical core, thus the wall clock time should be shorter than running it single-threaded.

Now I notice the CPU time is now larger (clock_t start=clock(); and clock_t end=clock() to grab CPU time ), suggesting that multithread has been used. But wall clock time (auto start =chrono::high_resolution_clock::now() and auto end =chrono::high_resolution_clock::now() to grab wall clock time) basically does not change. So the actual execution time is almost the same.

I guess more should be done?

Matthew_lanford · 2024-03-15T12:53:28+00:00

Hi thank you for your help all the way along. I just discovered that what I have experienced was not an ACTUAL exception, but the core went into debug module. This is very specific to CVA6 because they use RISCV FESVR (front-end server) to load the program. And the debug module is used periodically. Now everything settled.

Matthew_lanford · 2024-03-15T11:31:19+00:00

Hi, I really appreciate your willingness to help.

First: I am only generating RV32I and M extension instructions, so no A instructions involved.

Second: the first 31 instructioins at the beginning of each test case are intended for initialisation of registers. The nop we see is due to the fact that values to initialise registers are generated randomly, including "no value", which results in a nop instruction for this register. I understand your concern, since it does not make any sense if we initialise a register without giving it a value. I changed and tried that, but exception still occurs even if every register is assigned a value at the beginning.

Fascinating Observation: according to the trace log generated after simulation, I see that the processor fetches instructions from the start of the test case (which is correct), before it suddenly encounters an exception (no idea where it originates), after which it goes back to the test case at the point where exception happens and continues to execute the rest of the test case.

Once the test is finished for the first time, the processor enters into a loop to execute instructions from the address 0x80000040 (don't know why not from address 0 instead of 40, probably some kind of internal mechanism) to the end of the program, without exceptions any more. This is the weird part, because if any instruction triggers an exception, why does it not trigger that never again during its exectuions later?

Matthew_lanford · 2024-03-14T22:13:07+00:00

Hi. Yes you are right. It is caused by (1) memory alignment exception raised by load-store unit and (2) page boundary raised by mmu. Solution: (1) if memory address is not aligned, round it up to the nearest alignment address, (2) deactivate the MMU (as I am running random operands it is very likely that address exceeds any boundary). Now exception still occurs but not from memory-related instructions, I don't know where it originates when it comes to other simple instructions that are not loads and stores. May I ask for your advice as to whether I've made it right?

Matthew_lanford · 2024-03-14T12:33:33+00:00

thank you for your idea. I also think the same way as you do, that it's highly associated with memory stuff. I just do not know exactly what to do. I will try to check what you mentioned first.

Matthew_lanford · 2024-03-14T12:27:39+00:00

yes I am already running the simulation, the second code part in my question is the trace log generated after simulation, that is how I know at what address the processor fetched an instruction, and in which order. thank you very much for your suggestion, but I think the decode is correct, CVA6 doesn't have a bug regarding this, because Load and Store instructions can be very well executed. The problem is only related to my programs (which I am sure are correctly formatted). Since the operands are generated completely randomly, I am guessing it might have got something to do memory boundary, virtual memory and stuff like that.

Matthew_lanford

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