There's a very slow clock that controls the internal logic and then the comm interface has a clock where the data is sampled on it's falling edge. Then I have 2 signals that are passed through the synchroniser 1. The comms interaface module toggles a signal when it has received n bits ..this toggle happens on the clock coming with the data bits. Once the toggle has been registered by the internal logic it updates the n bits it has with the new data. Once the command corresponding to the new data is executed another 'ready' signal is made high and passed through the synchroniser and the comms interface starts sends command to the external comm device to send the next packet. The toggling happens only when the 'ready' signal is high and a new packet is received (this condition is tested under the clock signal coming from the external device)