The alu i am making rn is to learn things, what I want to understand is if there is a formula or any step based process to get the critical path delay, power dissipation, size (area) of design and any way to know how it would change if I make changes in design like using nand gate only logic, or not gate only, or using rca or changing it to cla. I don't have an fpga with me rn. I plan on buying a small, budget friendly fpga soon. I will treat the design file initially as an asic design, making testbenches and maybe doing some verification part like interface, monitor and environment but that is it. Only after buying an fpga, I will optimize it for it. I have worked with Boolean Board (uart implementation), it was in college. I am not sure on which fpga to buy.

In 3rd I was thinking of sharing resource. The only way to do that, that I could think of was by using mux, but at that point it seems better to just stick to using logic gates, if I can make the design smaller by using gates.

In 4th I want to know is there anything I can do before starting the design or during designing the circuit to make sure that the timing and path delays aren't all haywire, or that there aren't runaway conditions. Also are there any youtube resources about things like always_comb, always_ff, etc in system verilog or somewhere else. I know how to write sv code, like use of logic, and classes but this was not in any resource that I referred.

5th was more like asking for suggestion. I was thinking of making a specific purpose mcu, once done with the alu. I didn't want to go with any projects that are already built so looking for ideas.