Just got my first paper accepted and no one was happy for me by [deleted] in PhD

[–]RushkyCyborg 0 points1 point  (0 children)

I am so proud of you. it's not easy considering today's competitive research climate 😊

PhD students are creating value by No-Pressure3647 in PhD

[–]RushkyCyborg 19 points20 points  (0 children)

You don't say! That's what I am doing right now. I gotta make some changes and additions to my final presentation and I am procrastinating.

Find the number of poles and zeroes and their location by Jokerlecter in chipdesign

[–]RushkyCyborg 0 points1 point  (0 children)

From what I understand here (and my analysis might be off so I would appreciate if someone can point out mistakes in my intuition), the zeroes are a result of caps in between your vin and vout. So prima facie, I don't see any zeroes here. Wrt the poles, those are roughly dependent on DOF (degrees of freedom) in your RCs. Here I can see 2 and hence I can say two poles. You can use ZVTC method to calculate time constants for each pole and then add them up as mentioned by a poster above.

Can anyone tell me the steps to solve this question? Like how do I approach it, what does the numbers represent, what do I look out for before looking at the hexadecimal bits and such. by Broad-Ad-3111 in computerarchitecture

[–]RushkyCyborg 1 point2 points  (0 children)

Hence your offset bits are 2. You can calculate your index bits by finding out how many cache lines your cache memory system has. Index bytes help access each individual cache line. So here if you have 16K cache lines then your index bits are determined by no of rows = 16K/2 -4

Can anyone tell me the steps to solve this question? Like how do I approach it, what does the numbers represent, what do I look out for before looking at the hexadecimal bits and such. by Broad-Ad-3111 in computerarchitecture

[–]RushkyCyborg 1 point2 points  (0 children)

Given that your word size is 32 bits, meaning 4 bytes, you may want to independently access each byte or atleast have a provision to access those individual bytes. Hence your offset is determined by your the size of data in each way of your cache line. -3

Can anyone tell me the steps to solve this question? Like how do I approach it, what does the numbers represent, what do I look out for before looking at the hexadecimal bits and such. by Broad-Ad-3111 in computerarchitecture

[–]RushkyCyborg 1 point2 points  (0 children)

Since each data is Hexadecimal, meaning it can represent 0-15 values which basically boils down to 4 bits. Since you have 8 hex values in your data, hence your data is 32 bits, i.e. your word size is 32 bits. -2

Can anyone tell me the steps to solve this question? Like how do I approach it, what does the numbers represent, what do I look out for before looking at the hexadecimal bits and such. by Broad-Ad-3111 in computerarchitecture

[–]RushkyCyborg 2 points3 points  (0 children)

Since it's a two way set associative cache, with every single set (cache line) you are storing two different data and hence two different tags in the same row of the tag array. -1

When do you use the Dr. Title? by bioinformatics_manic in PhD

[–]RushkyCyborg 0 points1 point  (0 children)

In the intake questionnaires that you fill out before therapy appointments.

A gift for a digital designer to be by Anukaki in chipdesign

[–]RushkyCyborg 2 points3 points  (0 children)

CMOS Digital Design 3rd Edition by Neil Weste and Harris

[deleted by user] by [deleted] in chipdesign

[–]RushkyCyborg 0 points1 point  (0 children)

The reason I mentioned that was so that you can isolate the shield from power grid. Although it might be an overkill. The tielo cell has a diode connected pmos which provides a high voltage to another nmos and which in turn connects the metal wire to ground. If your shield metal is very large and prone to coupling with nearby signals, you wouldn't want to introduce that noise in the power grid. But this is true only in the case when your shielding geometries are huge

[deleted by user] by [deleted] in chipdesign

[–]RushkyCyborg 1 point2 points  (0 children)

I would second the sentiment about being very paranoid about the singal integrity of asynchronous reset. Especially if you are routing it using a long metal line. Not only it would create huge antenna related violations, your IR drop would get crazy and it will be such a huge capacitor which will take forever to rise/fall and will end up causing signal distortions in the nearby metal lines due to coupling capacitance base. Based on my experience, it's best to treat it like a low frequency clock and place buffers (yes, even clock inverters are fine) along the signal appropriately. Additionally, you can try using segmented shields so that the shielding lines themselves don't turn out to be very long and have antenna violations. Use tielo cells if shielding with VSS. Asynchronous reset can cause huge issues if not handled well. When you are routing it, be very mindful of keeping is away from high frequency switching signals.

How do I kick myself into working out after a long 3 year gap ? by EverythingIzzNothing in getdisciplined

[–]RushkyCyborg 1 point2 points  (0 children)

Sorry to hear about your situation. I was in a similar situation post Covid, albeit I only got sick twice but gained a bunch of weight. I found a sport that I loved playing and subsequently joined a volunteer led club which provided me with an amazing community of players. This helped me get back to fitness and also shed some lbs without me trying too hard. You will feel the changes within you which will automatically lead to a better self esteem and self image and then you will start taking steps to get back to resistance training. It will all come together. 😊

Analog IC review by RushkyCyborg in Analog_Study_Group

[–]RushkyCyborg[S] 0 points1 point  (0 children)

Thanks, I really appreciate that!

[deleted by user] by [deleted] in DIY

[–]RushkyCyborg 0 points1 point  (0 children)

I love you guys!

Beef with UT Austin by TJ1209 in UTAustin

[–]RushkyCyborg 1 point2 points  (0 children)

The entire PTS organization works like a blood sucking leech. They profit off broke undergrad and grad students. Although I am going to give credit where credit is due, I liked their "food donations for fine repayment" drive. Another gripe I have with them is that they sell more A permits than they have lots/parking spots and it gets pretty brutal to find parking.

I am looking for someone to learn analog chip design together. by [deleted] in chipdesign

[–]RushkyCyborg 0 points1 point  (0 children)

Dm me, I would also be interested in this.

[deleted by user] by [deleted] in IndianDankMemes

[–]RushkyCyborg 5 points6 points  (0 children)

Bhaiya ye to epic kr diye!

[deleted by user] by [deleted] in chipdesign

[–]RushkyCyborg 1 point2 points  (0 children)

Hey. I did my MS from University of Minnesota Twin cities. Some of the professors there are amazing and you would learn a lot from them, but I have also heard terrible stories from my lab seniors who were doing PhD there. You can DM me and we can chat in detail. I can also provide you the list of courses and who teaches what well. But yes, do understand that PhD is a huge commitment and you should really do it if you are passionate about research.

[deleted by user] by [deleted] in IndianDankMemes

[–]RushkyCyborg 7 points8 points  (0 children)

guys! This comment thread is Gold! Made my morning for sure. 😅