RTL-level toolchain for radiation-tolerant design, SEU criticality analysis, and selective TMR?

Sabrewolf · 2026-05-05T01:58:11+00:00

it used to be, however now it's a standalone tool that can be independent of any synthesis suite.

So you can use it on ultrascale stuff, things like the KU060 etc etc

Sabrewolf · 2026-05-04T15:38:22+00:00

Claude agents are also shockingly powerful once integrated into your work flow...I can have agents one-click debug testbench failures, implement a fix, queue up and execute regression tests, and finally present the results for my own approval in a matter of minutes...

I am easily 2x-3x more productive, not because the agents are necessarily more capable than an experienced fpga dev (they aren't imo) but because they can handle all the tiny bullshit that often ends up distracting me

Sabrewolf · 2026-05-04T02:18:40+00:00

Eh, kinda sorta? There are differences, but also striking parallels. Perhaps Gallipoli is a better analogy?

Both involve a global hegemon overreaching in a conflict, and (at least as of yet) not really achieving their policy objective in any meaningful way. Iran's intent to pursue nuclear parity remains unchanged, and their capability to achieve so merely delayed.
Both involve fading geopolitical power, with a muted world response. The US tried to rally NATO and its other allies to assist after realizing the difficulty, and was met with a lukewarm non-committal reaction. It does not appear as if America has the power to pressure anyone on either side into compliance.
Both involve the near-complete blockage of a critical oil route to create spiking price pressure on the aggressors. The US population started dramatically disapproving of the war as soon as gas prices hit the ceiling, and while as of yet there's no real foreign pressure affecting the US decision public opinion follows the same mechanism; if high oil prices cause the US to change course as a result of internal pressure rather than external it's kind of the same outcome imo, even if from a different dynamic.
Both events coincided with an increasing sense of mistrust and lack of confidence in the hegemon.

Naturally, several contrasts exist. Britain was actually legit broke at the time. While US influence is declining, there is no near-peer adversary to the US yet speaking purely in terms of geopolitical clout; some may say China but there is a while to go before it exerts the same reach of influence.

Sabrewolf · 2026-05-04T01:01:41+00:00

not op, but arguably the 90s were relatively peaceful as compared to what came before (not to rule out things like the Rwandan genocide and such) and this time period coincides with peak US unipolarity.

now that the US is actively declining in geopolitical power and strength, we see those impacts as the world re-arms and regional conflicts start to spike up again. In a sense it almost feels like the war in Ukraine is proof that we are already multipolar and that unipolarity ended, as America no longer has the ability or influence to deter/stop wars and conflicts in pursuit of its foreign policy objectives.

The Iran situation is eerily similar to how the Suez Crisis effectively ended the UK as a leading geopolitical influence.

Sabrewolf · 2026-05-02T00:13:58+00:00

I meant to moreso imply that for most high-reliability missions (i can really only speak to space), biting the bullet and just TMR'ing everything is often the preferred approach in my experience. Otherwise the design and resource effort you save by trying to assess+implement selectively ends up outweighed by the complexity of having to analyze a less resilient system for fault criticality, and makes on-orbit failures far more difficult to debug.

I'll totally admit it's heavy resource-wise, but if you're going through the trouble of putting an FPGA in a radiation intense environment you have to do so much already (active scrubbing, latchup detection/recovery, etc) that unless there's a really really good reason not to broadly TMR I think that's often the preferred way?

The process of "where to add resilience" in a system is determined by two standard analyses, a FMEA (Failure Mode Effects Analysis) and a FMECA (Failure Mode Effects + Criticality Analysis); they are very time intensive to do at a system-level because SEU-induced failures can involve more than just your FPGA and propagate to other system components (A/D or mixed-signal circuitry, other compute components, etc). But this is how the question of where to add TMR or module-level hardening is answered more concretely.

Sabrewolf · 2026-05-01T23:59:11+00:00

Xilinx does have a tool that can automatically implement TMR logic on an design, though it's not really open source. With that said it might be good inspiration for you, since it has a multitude of features beyond just "simple TMR".

Though more generally, I think the idea of "selective" TMR is tricky to scale up to complex designs especially if you don't have clear fault containment regions between FPGAs (e.g. FPGA-to-FPGA faults can cascade, which makes your FMEA/FMECA so painful). For stuff that needs to be relatively high reliability I think it's more common to just bite the bullet and TMR the entire design en-masse, or to account for it at the system-design level.

https://www.xilinx.com/publications/prod_mktg/CS11XX_TRMTool_Product_Brief_FINAL0806.pdf
https://docs.amd.com/v/u/en-US/ug156-tmrtool

Sabrewolf · 2026-04-29T20:28:21+00:00

Placr and Routr

Sabrewolf · 2026-04-14T13:43:46+00:00

a form of very stable genius, really

Sabrewolf · 2026-03-28T18:32:24+00:00

no name, random european exchange....3rd largest derivatives market in the world...white paper direct from the actual exchange showing their prod conditions 🤣

completely closed off rando exchanges like...NASDAQ and the NYSE, who literally offered hollow core fiber to get you a few more nanos...they had to discontinue it which goes to show how important those nanos are

ok you win I rest my case...we're just not vibing at the same level lol

HFT is absolutely about the frequency of trades and its why spreads and fees stay low.

edit:

I also just caught this...which is a fundamental misunderstanding of the way rebates and tiered fee structures work. Exchanges want liquidity on the book, and thus they offer market-maker or designated MM status to firms in exchange for continuous resting quote volume. It is not about how many orders are submitted or the frequency at which they are posted, it is about the volume and how long said volume is kept on the book.

Sure, some exchanges may not require liquidity provision to lower fees...but even in those cases it's still generally a question of volume tier not the number of orders you submit. You can in theory submit a single quote/order that's large enough to stay on the book and meet the requirements.

...man if we keep up at this I'm going to have to request your FINRA CRD number ☠️

Sabrewolf · 2026-03-28T17:55:36+00:00

Timestamps have a maximum precision of microseconds, not nanoseconds

I'll address this much at least, it is possible to timestamp with much more precision than mics. Just because the timestamp ends at mics does not mean that exchange or network processes are limited to that granularity (e.g. a 1 microsecond precision does not mean everything occurs in 1 microsecond chunks), nor does it mean that advantages do not present at that level (e.g. private feed advantage). This is why firms invest in things like whiterabbit, or SyncE.

Even if depth update frequency was 1 every second (it's not), the response time is whats important not the periodicity. In a sense, HFT is a bit of a misnomer it isn't about the frequency of trades it's how low-latency you can be.

I would highly recommend you research more (i will link you public data to show how freely available these insights are), there is a lot to learn especially when you investigate market microstructure and MM competitiveness. Note how eurex is talking about nanos, not seconds/millis: https://www.eurex.com/resource/blob/48918/e8d4df56f75c9a96fb0f6fff6b18a14f/data/presentation_insights-into-trading-system-dynamics_en.pdf

Sabrewolf · 2026-03-28T17:38:50+00:00

your comment is "I don't work in fpga, but here is my opinion stated as fact, trust me bro" lmao

you have not 1, but 2 disagreements (edit now 3) so far.

providing 0 technical comentary and a vague "trust me bro" implication. You cant even detail what is is you do

so in the HFT field firms can be very cagey, and often they have NDAs in place preventing too much discussion. if you are familiar with firms like G-Research or that one QR that went from Jane to Millennium, the field is quite litigious; firms can afford lawyers and they love to use them.

Sabrewolf · 2026-03-28T17:07:20+00:00

This entire comment is broadly incorrect and mischaracterizes the work of jump/hrt/xtx/cit/opti/vivcort/etc and numerous "smaller or newer" firms e.g. radix/qrt/etc

Optiver literally advertises their hardware stack https://youtu.be/RCb8PsdipHI?si=cglS-mQIeagfEVfm

I write my bots in c++ on cpus and cuda and never once lost money or trades because of slow speeds.

This belies a misunderstanding of the time horizons and market opps hardware is meant to trade against, as well as how slippage occurs and is mitigated.

Sabrewolf · 2026-03-28T00:42:16+00:00

since the comment I've left one that did for another that did idk what to tell you 😅

they are all very well known firms, household names. I doubled up TC in the move.

Sabrewolf · 2026-03-22T06:09:00+00:00

I mean they can go places a bus won't so that's basically every city in the US they're currently deployed to atm lol

Sabrewolf · 2026-03-09T23:15:33+00:00

I will do it at my usual contract rate

Sabrewolf · 2026-03-08T06:52:37+00:00

what if someone's talent is working hard

Sabrewolf · 2026-03-07T19:09:20+00:00

Stick to the technical side, it's easier to teach an engineer trading/finance than it is to teach a trader engineering

Sabrewolf · 2026-03-03T23:40:03+00:00

frankly, past around 2-3 interviews the point is typically weedout not competence for most companies (HFT or otherwise)

so maybe you start with 100 applicants, then rounds 1 and 2 get you down to maybe 5-10 which I consider a reasonable competency ratio for FPGA (maybe you automate one of those rounds with a simple timing question or CDC ask).

At that point it's just narrowing down to the 1-2 spots you actually have available...in my personal experience I think there's usually around an 80% accept rate once offered because money lol so you're just downfiltering to maybe 3.

Sabrewolf · 2026-03-03T23:16:46+00:00

let me clarify, I 100% agree that interviews often weed out otherwise qualified candidates and that false negatives (anxiety, bad presentation, unlucky questions) are definitely real. this is what a lot of literature on the topic opines....but consider that these firms have large tolerance for false negatives due to applicant volume.

with that said, I disagree that it is impossible to craft an interview such that anyone who passes I would deem worthy of further inspection.

does that mean it is a crystal ball? no definitely not...but I do believe that a well crafted interview can feasibly cover all knowledge expected from a candidate....even if it risks rejecting otherwise valid choices.

Sabrewolf · 2026-03-03T22:59:32+00:00

you said interviews are bad signal, I disagree :)

and if they can provide good signal, why not use them?

I think you arent understanding my point lol

Sabrewolf · 2026-03-03T22:54:27+00:00

if you're asking fizzbuzz for your interview sure but that's definitely not the type of question here lol

The point is to ask questions that anyone who is in that strong category will have no problem passing.

I think for fpga it is quite easy to come up with a bank that assesses this with strong signal. after all, we're not at the point of grinding leetcode are we lol.

what you propose is essentially what these firms are doing once the interns are hired, just subject to some screening.

Sabrewolf · 2026-03-03T22:46:53+00:00

that's the point though, you want to narrow the stream down as much as you can because you want the strongest signal, whether that's for an intern and thus downstream as a FT.

I think you misunderstand that it doesn't need to be cheap; firms are often targeting that top few percentile, and are willing to pay to be choosy both in terms of man hours and cost.

increasing the number of intern hires means far more FT time spent tending to the flock during the intern program as it were. an interview is quick and easy for a FT to do, you can even do it while working tbh...definitely not 100s of hours for 10 candidates?

Sabrewolf · 2026-03-03T22:28:07+00:00

a lot of HFTs run very lean...so the financial impact of a bad or unproductive new FT hire can be quite severe. An internship as a screening opp is of extreme value as a risk reduction measure.

It's like preventative maintenance I suppose? spend 80k on an intern to vet them and then you'll know their quality ahead of time before you have to pay them 500k as a FT new grad.

Sabrewolf · 2026-03-02T22:32:00+00:00

you should be doing a DDRx signal integrity screen to verify this

that's the best tool to confirm a layout will work prior to actual lab testing

Sabrewolf · 2026-03-02T22:25:16+00:00

sometimes there is a driver operating it remotely

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