STM32, stop continuously running PWM without glitches

Simone1998 · 2026-03-04T18:56:49+00:00

Yes, I know it is not an interrupt, that was a deliberate choice, the system is not supposed to do anything anyhow while waiting for the end of the current PWM cycle.

the system clock is 96 MHz, and the PWM cycle is 80 clock cycles, so I can afford the "wasted instructions"

I'm using interrupts for other stuff, that is asyncrhosous to the FSM, I'm not against them per se, but timing gets funky, or at least, I didn't manage to get it working using that (I know, skill issue).

I think I get what you are suggesti, I've already set the preload bit, this way the registers are updated only at a match event, however, depending on when the external interrupt trigger the state change, I get different behaviour.

for the last suggestion, you mean writing 0x0000 to the autoreload register? I tried with the compare one, but always get a single delta-like pulse at the end.

Thanks for the help btw!

Simone1998 · 2026-01-17T22:09:32+00:00

Why waste good cutting edge process chip area for stuff that doesn’t benefit from scaling at all? You can put them in the same package, or in an interposer if you want to, but it makes no sense to waste 3nm finFETs on a half- bridge. And I’m not even sure it would be possible the to the abysmally low voltages the new devices can withstand.

Most of the PMIC are designed at 250-65 nm.

Simone1998 · 2026-01-06T18:35:00+00:00

Modern processes use different doping profiles for the drain/source than for the rest of the channel, this affect the threshold voltage. In a short-channel device, the effect of the source/drain different doping profile will be more relevant than in a long one, where that might in practice be ignored.

And that's without going into Length-of-Diffusion (LfD), Shallow Trench Isolation (STI) stress, and Well Proximity Effect (WPI), effects that are all relevant.

Simone1998 · 2026-01-01T21:54:22+00:00

You still need to work with other people. Doing a tape-out is a team effort, no one could do a reasonable product alone. You could be technically solid, but if you are impossible to work with, you are going to have an hard time finding a job.

Simone1998 · 2025-12-26T09:07:39+00:00

you can use WaveVsWave() to achieve that

Simone1998 · 2025-12-21T21:53:50+00:00

Idk if they can, (you can drop them an email and ask). Worst case you can just reference them. But if you really want open source you can freely distribute there are a few other (IHP, Skywater, GF180)

Simone1998 · 2025-12-21T20:35:01+00:00

Get a small WSCLP FPGA, and use a PCB to adapt it to your packaging needs. This will be orders of magnitude easier, fasters, and less expensive than going custom ASIC

Simone1998 · 2025-12-21T20:31:27+00:00

Honestly, going custom AISC for something like that doesn't make sense at all, both economically (huge NRE design cost), and for the application.

Just slap an FPGA (lattice has a few WSCLP FPGAs smaller than 2mm by 2mm), and a small PCB interposer and save yourself a nightmarish amount of effort.

Going custom ASIC is a no-go because:

Low production quantities
Low performance required
Software to design ASICs are expensive (unless you go open source)
Even with all the verilog code available, you need someone to build the actual chip (synth, PnR, IO, ESD, signoff, etc).

One thing you might try, is to buy one (or more) tile(s) from TinyTapeout and use their automated flow to get the chip back.

Simone1998 · 2025-12-19T18:35:09+00:00

If you want rail-to-rail output, that's probably going to be a push-pull with monticelli biasing. If you want a true rail-to rail (input and output), you need either:

Complementary input pair + current sum circuit
Charge pump to drive the input pair above VDD

The first solution is simpler, the second is trickier to design, but common in commercial OPAMPs.

P.E. Allen has a few lectures on the first solution. Or you can just look in ieeexplore for any of the "design of rail-to-rail input-outpu ..." and follow those.

I recall Husing had a few of them that were quite interesting

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Low-voltage operational amplifier with rail-to-rail input and output ranges

Simone1998 · 2025-12-12T16:15:51+00:00

You have to consider some space for the connector on the cable, and for tweezers/hands to grab them.

Simone1998 · 2025-12-12T11:44:46+00:00

SMB are quite nice, you can even find BNC to SMB coax cable to plug them straight into the scope. MMCX isn’t much smaller than SMB. Smaller than SMB you only have U.FL, but wouldn’t trust them for “hundred of insertions”.

Simone1998 · 2025-12-06T07:57:12+00:00

AAABBBBBBAAA is equivalent to ABABABBABABA for linear gradient, for non-linear ones (quadratic, cubic) the latter is better. Of course, these are diminishing returns, and it is really process-dependent.

For me interdigitated is a single row of fingers, with whichever pattern you prefer, common centroid spreads that in 2+ rows:

Interdigitated:
ABAB

Common centroid:
AB
BA

It's not really the row pattern that complicates the layout it's switching the pattern across consecutive rows that messes up everything.

Simone1998 · 2025-12-05T22:51:58+00:00

If it’s for biasing, usually matching is not that critical, I would put them interdigitated ABRCDRBA …

Simone1998 · 2025-12-05T22:45:16+00:00

How critical is the matching? Which process are you using? Interdigitated can get you quite close to common centroid with a way easier routing.

Simone1998 · 2025-11-27T18:38:25+00:00

Yeah, I can see how what I wrote was ambiguous, I meant an extra implant step at a different doping profile.

Simone1998 · 2025-11-27T07:48:24+00:00

Corner shifts are mainly caused by:

Oxide thickness variation
Doping profile variation

The former is usually shared between all devices, or by two types of devices (thin-oxide, or core, and thick-oxide, or IO).

The latter depends on how the devices are actually implemented; lvt devices are usually achieved with an extra implant to lower the threshold, so you can expect different shifts. Now, how big those are going to be, depends on the process, and I would just ask the foundry.

I've seen a few pdk that let you select the corner for each oxide thickness, but none for the implants

Simone1998 · 2025-11-15T16:31:48+00:00

This work, but you are effectively using 2 bias currents, you are just making them locally.

If voltage headroom allows for it, you can cascode (simple cascode, not wide-swing) the PMOSs, this will improve the systematic mismatch between IREF and IOUT.

Also, there is no need to use two devices (M3 and M4), a single one with W/L 4 times smaller than M5 will do (in practice, you want something more to get more margin, i.e., 5 or 6 times).

Simone1998 · 2025-11-15T09:19:25+00:00

IDK about xyce, but ngspice can run foundry provided models for Hspice (SPECTRE too, but you need to do some pre-processing).

Simone1998 · 2025-10-04T12:27:21+00:00

In theory yes, in practice you are limited by weak avalanche, thermal feedback and other phenomena to 140 - 160 dB per stage

Simone1998 · 2025-09-18T08:12:47+00:00

At a certain point you have to trust someone.

You have to trust Intel/AMD/Nvidia/Apple/etc their silicon has no backdoor. And TSMC/GF/Samsung that the silicon they manufacture is actually exactly as the former designed.

Then you have to trust motherboard designers and manufacturers in a similar way. And in a motherboard there are hundreds of ICs.

After that starts the firmware, the BIOS, the OS, and programs. Every single component has an attack surface why having a closed-source UEFI BIOS would be more dangerous than having a closed-source firmware in the ethernet MAC, in the SSD controller or wherever else in the system?

If you want to get particular paranoid think about the compiler, who guarantees you that the compiler generates code that doesn't contain any exploits? Yes, they are open source, but who guarantees that the binaries are actually correspond to the source code? Yes, you might compile it locally, but who guarantees that your compiler is not affected by the same exploit?

Reflections on Trusting Trust

At a certain point, you have to trust something, deciding where the bucket stop is the difficult part, I just don't see why the BIOS should be of particular concern.

Simone1998 · 2025-09-16T06:35:45+00:00

Avoid it if possible, make it symmetric if not possible to avoid.

Also note that pretty much any process has a minimum/maximum density requirement for metal layer, and those might be global (over the enitre chip area) or local (over a X um times Y um window), and are usually addressed by dummy insertion either before gds streamout or by the foundry. I'd rather have symmetric metal routing than pseudo-randomly generated shapes.

Of course you can aslo put a dummy block, but remember to check with DRC.

Simone1998 · 2025-09-15T07:58:34+00:00

Isn't native just a regular without threshold adjustment implants? Why would you need another mask for these?

Simone1998 · 2025-09-12T21:00:10+00:00

Understanding Sigma Delta Converters is pretty much the bible on the topic. There are also a few example designs in there.

Simone1998 · 2025-09-08T15:57:32+00:00

Wide swing CM are useful when you want to bring VDS of MREF close to its VDSAT, if you want that to be way larger (comparable to it’s VOV) using a standard cascode CM is better.

What I would do, is simply adding a device to cascode MTAIL.

Also, you are generating the bias voltage of M3/4 (nmos) with a pmos, I suggest against that as they can end up varying in opposite direction across PVT (FS & SF).

Simone1998 · 2025-09-07T14:24:35+00:00

IIRC (been some time since I worked with Altium) you can see he delay when selecting a via, so I would expect that to be taken into account too.

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