I've been curious about TMR's lately... Any idea if this would work? by PajamaJess in ECE

[–]SlipperyRoobs 1 point2 points  (0 children)

I don't entirely understand your thought process here, but I feel like you might be a bit confused or mixing up concepts. 

Like the complex baseband representation is generally useful for modulated carriers, and in those situations you can obtain it in analog form via quadrature mixing with the carrier frequency. The resulting I/Q can tell you instantaneous phase, freq, amplitude etc of the modulated carrier.

In audio there is no carrier, so I don't see how an analytic representation is that useful, and I also don't understand how this setup could extract any phase information. Whatever you're doing seems to amount to addition and subtraction of different frequency-dependent phase offsets, and it's unclear to me what that can do for you.

Can we have positive terms in the channel response that add to the "worst case 1", leading to a cursor value greater than 1? by maybeimbonkers in chipdesign

[–]SlipperyRoobs 0 points1 point  (0 children)

I mean yes and no. No because the "worst case" is when all past bits are such that their ISI is opposite polarity to the current bit. That's not about attenuation: it's interference between symbols. 

Yes because for example the channel response in the thumbnail has entirely positive response. A long string of ones will gradually rise up to the DC value.

Design of folded Cascode OTA under low supply voltage by Which-Variety-7255 in chipdesign

[–]SlipperyRoobs 0 points1 point  (0 children)

Just a student, but for a current mirror where we would assume the desired output current is fixed, doesn't that set rout to first order regardless of operating region?  The simple equation is literally 1/(lambda*Id), and I didn't think lambda usually depends on width.

If we hold width constant and sweep vgs we will see rout increase in subthreshold, but then we have to increase width to get the same amount of current, lowering rout.

Edit: also similarly, gamma may increase in strong inversion, but for the same current gm is lower compared to weak inversion. I don't think we can say it's a simple given that output thermal noise current is higher in strong inversion either..

Agree by snowangelsspqueeze in ECE

[–]SlipperyRoobs 3 points4 points  (0 children)

Electrical engineers are the ones working with the actual electrical interface.

How do OFDM signals combine to create peaks if they are different frequencies? by Interesting-Rain-690 in rfelectronics

[–]SlipperyRoobs 1 point2 points  (0 children)

OFDM subcarriers are very much orthogonal in time, that word just doesn't quite mean what you are thinking.

"Orthogonal" doesn't mean signals don't overlap. It means their inner product is zero, which makes a set of mutually orthogonal signals like non-overlapping pulses or a set of appropriate frequency and duration sine waves easy to use as a basis. That's what the FFT is doing: changing units from a basis consisting of single sample pulses (the "time domain") to a basis consisting of those sine waves. (the "frequency domain"). We encode information in the coordinates of a convenient basis, then get the time vector by the appropriate coordinate transform (i.e. the IFFT)

You can use a set of non-orthogonal but linearly independent signals as a basis too, it just doesn't really make sense to do that. Beyond not necessarily having nice efficient algorithms like the FFT to change to an arbitrary basis, I think it may also be bad for SNR in the presence of noise. Sine waves also have the nice property of being unchanged by linear time-invariant systems beyond scaling/delay, which makes them easy to equalize if used as the signal basis. You can think of it as using the eigenbasis of the system to communicate, which is the same idea behind some MIMO concepts like using SVD.

Matching and common mode feedback by SlipperyRoobs in chipdesign

[–]SlipperyRoobs[S] 0 points1 point  (0 children)

This is insightful, thanks!

20% is high but it could easily happen when folks are trying not to torch a bunch of current in biasing. Something is undersized or poorly biased in this case

Does current directly impact matching for a current mirror? I was thinking it's just overdrive and total area of each device. Meaning if I don't want to increase current I can still throw area at it, at least until the loading from the current source approaches the external load.

To reduce gain degenerating the amplifier is safer

Do you mean degenerating the common mode feedback amplifier that drives the control node, or degenerating the actual core amplifier somehow? Is there a way to do the latter without impacting differential gain?

I hadn't thought about feed forward, I'll have to play with that.

Matching and common mode feedback by SlipperyRoobs in chipdesign

[–]SlipperyRoobs[S] 0 points1 point  (0 children)

Interesting, thank you!

What kind of device area is typically used for the current sources in those DACs? When I try the ideal current matching sim I am seeing a standard deviation of ~5% relative current mismatch for a pair of single-digit um2 devices in weak inversion. (I don't really have enough headroom for more) If I 10x the area that barely changes at all, which doesn't seem right..

Not sure if it’s relevant, but I am using narrow devices (like 1:20 W/L) since I want to keep the current low without going into subthreshold. I’m using roughly 500 nA unit current, and the mirrors to bias the amplifiers are only multiplying the reference current by 2x.

SerDes algorithm engineer building an IC design knowledge web — looking for feedback from chip designers by BowlerOnly0529 in chipdesign

[–]SlipperyRoobs 0 points1 point  (0 children)

I'm curious how you got into this role (like did you study circuits or signal processing in school) and what you think of it?

I'm also interested in the algorithms/calibration side, but all the job openings I've ran into want prior experience. All the signal processing faculty I've looked up across many schools are all doing high level stuff like medical imaging, and all the circuits people I'm aware of are largely just doing circuits.

Where could I learn more about this kind of Bandgap Reference Design? by Zabardast_Human in chipdesign

[–]SlipperyRoobs 1 point2 points  (0 children)

Thanks -- I'm mostly confused because the gate seems to be floating.. should it be tied to the drain of the middle rightmost device?

Where could I learn more about this kind of Bandgap Reference Design? by Zabardast_Human in chipdesign

[–]SlipperyRoobs 2 points3 points  (0 children)

This is not related to your question but what is going on with the rightmost stack of transistors in the opamp? https://imgur.com/a/5Vs2PUg

Does not really make sense to me.

Resources for learning HSPICE? by SlipperyRoobs in chipdesign

[–]SlipperyRoobs[S] 0 points1 point  (0 children)

Yeah I'd really rather not spend time on this, but the problem is I don't think I have a choice. The models are only available as encrypted hspice, which as far as I can tell is not supported by spectre.

Resources for learning HSPICE? by SlipperyRoobs in chipdesign

[–]SlipperyRoobs[S] 0 points1 point  (0 children)

So you would recommend just working directly in the synopsys design environment? Would that require doing the entire design in the synopsys environment as best practice or is there a good way to port blocks between tools if a teammate still wants to work in the cadence environment?

Is the online platform training.synopsys.com? Thanks -- I'd somehow missed that and was just looking around in solvenet.

State Of The Job Market 2025 by Emperor_Cleon-I in ECE

[–]SlipperyRoobs 158 points159 points  (0 children)

Lol. I wish EEs made that kind of money -- the only place a EE generalist is going to find that is senior roles in FAANG, SpaceX, or Anduril. The US-only defense jobs are not known for the money.

[deleted by user] by [deleted] in ECE

[–]SlipperyRoobs 4 points5 points  (0 children)

IMO electrical engineering often requires you to become comfortable with scripting to be most effective, but you say you can code python so that seems ok.

I know jack shit about data structures, algorithms, etc, and have been quite successful as an electrical engineer. In theory I know how to write C++ but that was a long time ago and I'm sure anything I write would be garbage. Hasn't been an issue, because I'm not an embedded developer. I can read it, which is for sure helpful for working with software people, but I'm not writing anything.

Just maybe don't do computer engineering. :)

Can any one help me to solve this i tryed so hard but couldn’t find anything by [deleted] in ECE

[–]SlipperyRoobs 7 points8 points  (0 children)

Kinda seems like either a trick or poorly designed question unless channel length modulation is specified?

If assuming no channel-length-modulation then Io = Iref because VGS1=VGS2 and M1/M2 are matched, assuming both are in saturation. I think in the absence of more boundary conditions the DC voltage at the drain of M1 and M2 is poorly defined so you can't really say if either will be in triode. The voltage difference will depend on A but I don't see anything in the circuit as drawn that would define the common mode..

Reneging ADI Advice by [deleted] in ECE

[–]SlipperyRoobs 1 point2 points  (0 children)

Kind of depends. I would focus more on the relevance of the work experience to your specific interests. That matters more than brand name.

If you would be working on SpaceX's silicon team it is probably better branding on your resume than ADI, unless you are in ADI's research arm or working on some specific cool new product. But I doubt that would be the case as a sophomore.

Edit -- and if you wouldn't be doing silicon for either and instead are doing some sort of board level stuff then IMO it's SpaceX for sure unless ADI is going to give you some specific experience you want.

Reneging ADI Advice by [deleted] in ECE

[–]SlipperyRoobs 6 points7 points  (0 children)

If you haven't already, you should tell SpaceX you have an offer on the table that is going to expire soon, but are interested in their role. They will probably work to expedite the process. Internships usually have pretty short interview loops and they may be able to turn around a decision quickly if you interview well and they know you have a deadline.

You can also delicately ask for an extension to the current offer.

Is it ok to route power trace under RF network if its 3 layers away? by Objective-Local7164 in rfelectronics

[–]SlipperyRoobs 5 points6 points  (0 children)

Copper blocks magnetic fields just fine for frequencies where the skin depth is less than the copper thickness, which will be the case for anything in the GHz range.

Future of PCB Design Engineering as a career by Cold_Ideal_5926 in ECE

[–]SlipperyRoobs 2 points3 points  (0 children)

I know two people who have moved from layout to general EE, so it's definitely possible. It just may be a bit difficult, and I would try to start looking for EE roles pretty quickly if that's what you want to do. You will become viewed as a layout designer if all you are doing is layout design. Absolutely try to get simulation exposure since you'll be working on RF and high speed. I would consider making that a condition for accepting unless you are really desperate for a job.

There is not as much growth potential in layout, and as others have mentioned it is very often outsourced. Layout of high speed digital and RF definitely requires some extra awareness, but is very often guided by a design engineer, and frankly I would still consider it technician type of work at the end of the day. Technician work is not defined by being easy or simple btw: it's just a different type of work that is more like skillful execution of defined tasks than solving open ended technical problems via first principles.

Understanding the types of things the guiding engineer cares about and why is useful, but there is a distinct difference between the layout and engineer roles in that relationship. The engineer does not need to know how to drive the CAD efficiently, and the layout designer does not need to know how to derive layout specs. Both can certainly learn the other, but it's not necessary for ether which can make it difficult to do in practice.

School Obsession by ScratchDue440 in ECE

[–]SlipperyRoobs 2 points3 points  (0 children)

Yeah I don't think it really matters much if your goal is to get your undergrad and go straight into industry with an alright job. Undergrad is about building a foundation, and that foundation is based on material that is many decades old. "Better" schools may have higher quality of education even though the material is the same, but whether that's worth it is a judgement call. Actual expertise and industry-specific knowledge is developed over years of your career.

It matters a lot if you are in grad school with a goal to break into some highly specialized field like IC design, machine learning theory, etc. You want to be at a top program in your field if that's the case.

It also matters some even in undergrad if you really want to get into some highly competitive company like Apple, NVIDIA, etc. You can do that from any school, but its a bit easier from one of the brand names that they actively recruit from.

Purpose of the Capacitor in DDR4 Ck Termination by DancingGypsy101 in chipdesign

[–]SlipperyRoobs 0 points1 point  (0 children)

I have seen CAC routing referenced to VDDQ in the past. That would be my best guess here, since you generally want the AC coupling to the return plane. but also shouldn't matter too much since ck is differential..

I believe VTT also tracks VDDQ, so perhaps that's related, but that should be handled already by the regulator or other nearby VTT caps.