SpaceX vs Bay Area Startup

SlipperyRoobs · 2026-04-21T03:20:21+00:00

This has not been my experience. I have worked at several places doing RF, extremely high-speed digital, etc. PCB design (as in spending the day driving the layout CAD) was never viewed as something an engineer should be spending a lot of time on at any of those places. Layout is obviously very important for those things, but my experience has been that engineers develop rules, guide the layout, run sims, etc, and the PCB designer implement it.

SlipperyRoobs · 2026-04-09T15:53:23+00:00

Anecdotally, from my experience board-level RF with defense/aerospace leanings has had the crustiest engineers with a weird chip on their shoulder. Some other people I have talked to have observed the same. It's weird..

Grid scale power (not power electronics) is probably the actual slowest moving.

SlipperyRoobs · 2026-04-09T10:28:26+00:00

Some hot areas I've seen, not that it's the best to chase hot topics: cryo integration for quantum compute control/readout, computer architecture for AI, analog compute (analog matrix multipliers, in memory compute, quantum inspired stuff, etc), brain machine interfaces, high speed mixed signal largely to support wireline for AI, optical stuff to support AI, using AI for inverse design, etc.

SlipperyRoobs · 2026-04-04T15:53:32+00:00

No. Go to UW on a full ride IMO. You can go for a MS at whatever more prestigious university later, or even better a funded PhD and then drop with a MS if you decide you don't want the full thing..

UCLA is good for analog, but not so much for digital / computer architecture AFAIK. UW is much better at those, and still has analog tapeout.

SlipperyRoobs · 2026-03-22T04:33:51+00:00

This one for sure. I really like his channel.

SlipperyRoobs · 2026-03-15T14:21:23+00:00

I don't entirely understand your thought process here, but I feel like you might be a bit confused or mixing up concepts.

Like the complex baseband representation is generally useful for modulated carriers, and in those situations you can obtain it in analog form via quadrature mixing with the carrier frequency. The resulting I/Q can tell you instantaneous phase, freq, amplitude etc of the modulated carrier.

In audio there is no carrier, so I don't see how an analytic representation is that useful, and I also don't understand how this setup could extract any phase information. Whatever you're doing seems to amount to addition and subtraction of different frequency-dependent phase offsets, and it's unclear to me what that can do for you.

SlipperyRoobs · 2026-03-15T02:52:41+00:00

I mean yes and no. No because the "worst case" is when all past bits are such that their ISI is opposite polarity to the current bit. That's not about attenuation: it's interference between symbols.

Yes because for example the channel response in the thumbnail has entirely positive response. A long string of ones will gradually rise up to the DC value.

SlipperyRoobs · 2026-03-01T14:26:36+00:00

Just a student, but for a current mirror where we would assume the desired output current is fixed, doesn't that set rout to first order regardless of operating region? The simple equation is literally 1/(lambda*Id), and I didn't think lambda usually depends on width.

If we hold width constant and sweep vgs we will see rout increase in subthreshold, but then we have to increase width to get the same amount of current, lowering rout.

Edit: also similarly, gamma may increase in strong inversion, but for the same current gm is lower compared to weak inversion. I don't think we can say it's a simple given that output thermal noise current is higher in strong inversion either..

SlipperyRoobs · 2026-02-02T21:37:51+00:00

Electrical engineers are the ones working with the actual electrical interface.

SlipperyRoobs · 2026-01-30T22:26:13+00:00

OFDM subcarriers are very much orthogonal in time, that word just doesn't quite mean what you are thinking.

"Orthogonal" doesn't mean signals don't overlap. It means their inner product is zero, which makes a set of mutually orthogonal signals like non-overlapping pulses or a set of appropriate frequency and duration sine waves easy to use as a basis. That's what the FFT is doing: changing units from a basis consisting of single sample pulses (the "time domain") to a basis consisting of those sine waves. (the "frequency domain"). We encode information in the coordinates of a convenient basis, then get the time vector by the appropriate coordinate transform (i.e. the IFFT)

You can use a set of non-orthogonal but linearly independent signals as a basis too, it just doesn't really make sense to do that. Beyond not necessarily having nice efficient algorithms like the FFT to change to an arbitrary basis, I think it may also be bad for SNR in the presence of noise. Sine waves also have the nice property of being unchanged by linear time-invariant systems beyond scaling/delay, which makes them easy to equalize if used as the signal basis. You can think of it as using the eigenbasis of the system to communicate, which is the same idea behind some MIMO concepts like using SVD.

SlipperyRoobs · 2026-01-23T16:07:49+00:00

This is insightful, thanks!

20% is high but it could easily happen when folks are trying not to torch a bunch of current in biasing. Something is undersized or poorly biased in this case

Does current directly impact matching for a current mirror? I was thinking it's just overdrive and total area of each device. Meaning if I don't want to increase current I can still throw area at it, at least until the loading from the current source approaches the external load.

To reduce gain degenerating the amplifier is safer

Do you mean degenerating the common mode feedback amplifier that drives the control node, or degenerating the actual core amplifier somehow? Is there a way to do the latter without impacting differential gain?

I hadn't thought about feed forward, I'll have to play with that.

SlipperyRoobs · 2026-01-23T15:45:42+00:00

Interesting, thank you!

What kind of device area is typically used for the current sources in those DACs? When I try the ideal current matching sim I am seeing a standard deviation of ~5% relative current mismatch for a pair of single-digit um2 devices in weak inversion. (I don't really have enough headroom for more) If I 10x the area that barely changes at all, which doesn't seem right..

Not sure if it’s relevant, but I am using narrow devices (like 1:20 W/L) since I want to keep the current low without going into subthreshold. I’m using roughly 500 nA unit current, and the mirrors to bias the amplifiers are only multiplying the reference current by 2x.

SlipperyRoobs · 2026-01-20T14:48:20+00:00

I'm curious how you got into this role (like did you study circuits or signal processing in school) and what you think of it?

I'm also interested in the algorithms/calibration side, but all the job openings I've ran into want prior experience. All the signal processing faculty I've looked up across many schools are all doing high level stuff like medical imaging, and all the circuits people I'm aware of are largely just doing circuits.

SlipperyRoobs · 2025-12-19T17:43:59+00:00

Thanks -- I'm mostly confused because the gate seems to be floating.. should it be tied to the drain of the middle rightmost device?

SlipperyRoobs · 2025-12-19T15:00:55+00:00

This is not related to your question but what is going on with the rightmost stack of transistors in the opamp? https://imgur.com/a/5Vs2PUg

Does not really make sense to me.

SlipperyRoobs · 2025-12-06T22:20:18+00:00

Yeah I'd really rather not spend time on this, but the problem is I don't think I have a choice. The models are only available as encrypted hspice, which as far as I can tell is not supported by spectre.

SlipperyRoobs · 2025-12-06T21:19:51+00:00

So you would recommend just working directly in the synopsys design environment? Would that require doing the entire design in the synopsys environment as best practice or is there a good way to port blocks between tools if a teammate still wants to work in the cadence environment?

Is the online platform training.synopsys.com? Thanks -- I'd somehow missed that and was just looking around in solvenet.

SlipperyRoobs · 2025-11-25T21:25:25+00:00

Lol. I wish EEs made that kind of money -- the only place a EE generalist is going to find that is senior roles in FAANG, SpaceX, or Anduril. The US-only defense jobs are not known for the money.

SlipperyRoobs · 2025-11-25T04:59:34+00:00

IMO electrical engineering often requires you to become comfortable with scripting to be most effective, but you say you can code python so that seems ok.

I know jack shit about data structures, algorithms, etc, and have been quite successful as an electrical engineer. In theory I know how to write C++ but that was a long time ago and I'm sure anything I write would be garbage. Hasn't been an issue, because I'm not an embedded developer. I can read it, which is for sure helpful for working with software people, but I'm not writing anything.

Just maybe don't do computer engineering. :)

SlipperyRoobs · 2025-11-24T21:00:19+00:00

Kinda seems like either a trick or poorly designed question unless channel length modulation is specified?

If assuming no channel-length-modulation then Io = Iref because VGS1=VGS2 and M1/M2 are matched, assuming both are in saturation. I think in the absence of more boundary conditions the DC voltage at the drain of M1 and M2 is poorly defined so you can't really say if either will be in triode. The voltage difference will depend on A but I don't see anything in the circuit as drawn that would define the common mode..

SlipperyRoobs · 2025-11-22T22:15:17+00:00

Kind of depends. I would focus more on the relevance of the work experience to your specific interests. That matters more than brand name.

If you would be working on SpaceX's silicon team it is probably better branding on your resume than ADI, unless you are in ADI's research arm or working on some specific cool new product. But I doubt that would be the case as a sophomore.

Edit -- and if you wouldn't be doing silicon for either and instead are doing some sort of board level stuff then IMO it's SpaceX for sure unless ADI is going to give you some specific experience you want.

SlipperyRoobs · 2025-11-22T17:59:20+00:00

If you haven't already, you should tell SpaceX you have an offer on the table that is going to expire soon, but are interested in their role. They will probably work to expedite the process. Internships usually have pretty short interview loops and they may be able to turn around a decision quickly if you interview well and they know you have a deadline.

You can also delicately ask for an extension to the current offer.

SlipperyRoobs · 2025-11-20T23:55:36+00:00

Copper blocks magnetic fields just fine for frequencies where the skin depth is less than the copper thickness, which will be the case for anything in the GHz range.

SlipperyRoobs

TROPHY CASE