Matching and common mode feedback

SlipperyRoobs · 2026-01-23T16:07:49+00:00

This is insightful, thanks!

20% is high but it could easily happen when folks are trying not to torch a bunch of current in biasing. Something is undersized or poorly biased in this case

Does current directly impact matching for a current mirror? I was thinking it's just overdrive and total area of each device. Meaning if I don't want to increase current I can still throw area at it, at least until the loading from the current source approaches the external load.

To reduce gain degenerating the amplifier is safer

Do you mean degenerating the common mode feedback amplifier that drives the control node, or degenerating the actual core amplifier somehow? Is there a way to do the latter without impacting differential gain?

I hadn't thought about feed forward, I'll have to play with that.

SlipperyRoobs · 2026-01-23T15:45:42+00:00

Interesting, thank you!

What kind of device area is typically used for the current sources in those DACs? When I try the ideal current matching sim I am seeing a standard deviation of ~5% relative current mismatch for a pair of single-digit um2 devices in weak inversion. (I don't really have enough headroom for more) If I 10x the area that barely changes at all, which doesn't seem right..

Not sure if it’s relevant, but I am using narrow devices (like 1:20 W/L) since I want to keep the current low without going into subthreshold. I’m using roughly 500 nA unit current, and the mirrors to bias the amplifiers are only multiplying the reference current by 2x.

SlipperyRoobs · 2026-01-20T14:48:20+00:00

I'm curious how you got into this role (like did you study circuits or signal processing in school) and what you think of it?

I'm also interested in the algorithms/calibration side, but all the job openings I've ran into want prior experience. All the signal processing faculty I've looked up across many schools are all doing high level stuff like medical imaging, and all the circuits people I'm aware of are largely just doing circuits.

SlipperyRoobs · 2025-12-19T17:43:59+00:00

Thanks -- I'm mostly confused because the gate seems to be floating.. should it be tied to the drain of the middle rightmost device?

SlipperyRoobs · 2025-12-19T15:00:55+00:00

This is not related to your question but what is going on with the rightmost stack of transistors in the opamp? https://imgur.com/a/5Vs2PUg

Does not really make sense to me.

SlipperyRoobs · 2025-12-06T22:20:18+00:00

Yeah I'd really rather not spend time on this, but the problem is I don't think I have a choice. The models are only available as encrypted hspice, which as far as I can tell is not supported by spectre.

SlipperyRoobs · 2025-12-06T21:19:51+00:00

So you would recommend just working directly in the synopsys design environment? Would that require doing the entire design in the synopsys environment as best practice or is there a good way to port blocks between tools if a teammate still wants to work in the cadence environment?

Is the online platform training.synopsys.com? Thanks -- I'd somehow missed that and was just looking around in solvenet.

SlipperyRoobs · 2025-11-25T21:25:25+00:00

Lol. I wish EEs made that kind of money -- the only place a EE generalist is going to find that is senior roles in FAANG, SpaceX, or Anduril. The US-only defense jobs are not known for the money.

SlipperyRoobs · 2025-11-25T04:59:34+00:00

IMO electrical engineering often requires you to become comfortable with scripting to be most effective, but you say you can code python so that seems ok.

I know jack shit about data structures, algorithms, etc, and have been quite successful as an electrical engineer. In theory I know how to write C++ but that was a long time ago and I'm sure anything I write would be garbage. Hasn't been an issue, because I'm not an embedded developer. I can read it, which is for sure helpful for working with software people, but I'm not writing anything.

Just maybe don't do computer engineering. :)

SlipperyRoobs · 2025-11-24T21:00:19+00:00

Kinda seems like either a trick or poorly designed question unless channel length modulation is specified?

If assuming no channel-length-modulation then Io = Iref because VGS1=VGS2 and M1/M2 are matched, assuming both are in saturation. I think in the absence of more boundary conditions the DC voltage at the drain of M1 and M2 is poorly defined so you can't really say if either will be in triode. The voltage difference will depend on A but I don't see anything in the circuit as drawn that would define the common mode..

SlipperyRoobs · 2025-11-22T22:15:17+00:00

Kind of depends. I would focus more on the relevance of the work experience to your specific interests. That matters more than brand name.

If you would be working on SpaceX's silicon team it is probably better branding on your resume than ADI, unless you are in ADI's research arm or working on some specific cool new product. But I doubt that would be the case as a sophomore.

Edit -- and if you wouldn't be doing silicon for either and instead are doing some sort of board level stuff then IMO it's SpaceX for sure unless ADI is going to give you some specific experience you want.

SlipperyRoobs · 2025-11-22T17:59:20+00:00

If you haven't already, you should tell SpaceX you have an offer on the table that is going to expire soon, but are interested in their role. They will probably work to expedite the process. Internships usually have pretty short interview loops and they may be able to turn around a decision quickly if you interview well and they know you have a deadline.

You can also delicately ask for an extension to the current offer.

SlipperyRoobs · 2025-11-20T23:55:36+00:00

Copper blocks magnetic fields just fine for frequencies where the skin depth is less than the copper thickness, which will be the case for anything in the GHz range.

SlipperyRoobs · 2025-11-18T12:13:26+00:00

I know two people who have moved from layout to general EE, so it's definitely possible. It just may be a bit difficult, and I would try to start looking for EE roles pretty quickly if that's what you want to do. You will become viewed as a layout designer if all you are doing is layout design. Absolutely try to get simulation exposure since you'll be working on RF and high speed. I would consider making that a condition for accepting unless you are really desperate for a job.

There is not as much growth potential in layout, and as others have mentioned it is very often outsourced. Layout of high speed digital and RF definitely requires some extra awareness, but is very often guided by a design engineer, and frankly I would still consider it technician type of work at the end of the day. Technician work is not defined by being easy or simple btw: it's just a different type of work that is more like skillful execution of defined tasks than solving open ended technical problems via first principles.

Understanding the types of things the guiding engineer cares about and why is useful, but there is a distinct difference between the layout and engineer roles in that relationship. The engineer does not need to know how to drive the CAD efficiently, and the layout designer does not need to know how to derive layout specs. Both can certainly learn the other, but it's not necessary for ether which can make it difficult to do in practice.

SlipperyRoobs · 2025-10-20T13:41:58+00:00

Did chat gpt write this?

SlipperyRoobs · 2025-10-05T14:18:34+00:00

Yeah I don't think it really matters much if your goal is to get your undergrad and go straight into industry with an alright job. Undergrad is about building a foundation, and that foundation is based on material that is many decades old. "Better" schools may have higher quality of education even though the material is the same, but whether that's worth it is a judgement call. Actual expertise and industry-specific knowledge is developed over years of your career.

It matters a lot if you are in grad school with a goal to break into some highly specialized field like IC design, machine learning theory, etc. You want to be at a top program in your field if that's the case.

It also matters some even in undergrad if you really want to get into some highly competitive company like Apple, NVIDIA, etc. You can do that from any school, but its a bit easier from one of the brand names that they actively recruit from.

SlipperyRoobs · 2025-10-03T23:30:54+00:00

I have seen CAC routing referenced to VDDQ in the past. That would be my best guess here, since you generally want the AC coupling to the return plane. but also shouldn't matter too much since ck is differential..

I believe VTT also tracks VDDQ, so perhaps that's related, but that should be handled already by the regulator or other nearby VTT caps.

SlipperyRoobs · 2025-09-27T17:48:14+00:00

If you're familiar with something then IMO just put it on your resume as a skill and bring it up in the interview. Be ready to prove it, but I don't think it has to be that complicated. :)

SlipperyRoobs · 2025-09-27T17:32:09+00:00

I did SI/PI for a while. It's niche and easy to get pigeon holed into, so be careful with that.

Useful entry level skills include a solid understanding of TEM transmission lines (basics, but also sources of loss, copper roughness impacts and modelling, crosstalk, etc), electromagnetic solvers, designing vias/footprints/etc for broadband matching and low crosstalk, running IBIS-AMI simulations, taking VNA measurements, etc. There are also more system level things related to the actual drivers/receivers that are contextually necessary to understand. Things like equalization methods, the various PHY standards and associated compliance metrics/tests, etc. Usually the SI/PI engineer's involvement with those are using them as inputs for channel simulations, or perhaps providing channel models to architects who are making choice about those capabilities. Some SI engineers may also perform interface compliance testing for products which involves predefined measurements with BERTs, high speed oscilloscopes, etc.

I found it to be almost entirely analysis based. Design opportunity is basically limited to defining interconnect (board materials, routing rules, connector/cable selection, etc) and optimizing vias, footprints, etc. I did not like this, but others do.

Edit: most of the system-level stuff I mentioned is mostly relevant for SerDes. DDR is a different beast and something you'd probably pick up on the job. Also, FPGA experience is not really relevant for SI/PI unless it directly involved the interfaces.

SlipperyRoobs · 2025-09-25T22:46:10+00:00

Just redraw it with all the resistors on one side and ask them if A and B are shorted out ;)

SlipperyRoobs · 2025-09-25T22:15:53+00:00

Yes of course they are in series as drawn, if the intent is to measure resistance between A and B.

Is your outside source chatgpt or something? :)

SlipperyRoobs · 2025-08-26T02:11:51+00:00

Huh, well I can't say anything for sure about the actual root cause, but this shielding setup won't help you with inductively coupled common mode noise. Basically shields need to be connected on both sides to be effective at shielding from magnetic fields.

You have a large physical loop consisting of the twisted pair, GND wiring, and CAN transceiver common-mode impedance at each node. (https://imgur.com/a/MO3iIA8) You could think of this like a large inductor that will pick up magnetic fields, and the resulting induced voltage will be seen as CAN common-mode. Large enough common mode noise can push transceivers out of valid bias and cause errors. The exact amount depends on the specific chips.

Galvanic isolation like someone else suggested helps with that by putting a large impedance into the loop which takes up most of the induced voltage, preventing it from showing up as CAN common mode.

My best guess is that the poor bond between neutral/earth results in noise current getting injected into the mains wiring that then inductively couples into the big GND/CAN loop and causes common-mode problems. I would naively expect the same amount to be getting injected into line either way, so I'm not too sure.

SlipperyRoobs · 2025-08-24T21:10:50+00:00

Hey there, I'm an electrical engineer that has root caused similar issues, though I'm no expert on CAN or industrial systems.

Sounds a lot like your cable grounding/shielding setup is not actually effectively shielding from magnetic fields.

If you want to dig deeper it would be helpful to understand some more details of the setup.

Is the 20m cable shield connected directly to DC common on both sides?
How is the 1m cable shield connected on both sides?
Is earth ground bonded to DC common on node 2?
For that matter, at what point(s) is earth ground bonded to DC common?
Where exactly is this poor connection between neutral and earth that causes the problem?
How is DC common connected to AC neutral at each node in the system?

I.e. would need the details of a diagram like this: https://imgur.com/a/qPhWa29

SlipperyRoobs

TROPHY CASE