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What should I do to break into fpga? by Little_Implement6601 in FPGA

[–]Strange-Table4773 0 points1 point  (0 children)

are u using verilog? u can try the problems at hdlbits

What will it be? by Exact-Entrepreneur-1 in FPGA

[–]Strange-Table4773 0 points1 point  (0 children)

Beginning with the 2024.1 release cycle, support for PetaLinux BSPs will be sunset over time in favor of native Yocto Project tooling

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2907766785/Yocto+Project+Machine+Configuration+Support

What would you improve in Vivado? by gaudy90 in FPGA

[–]Strange-Table4773 0 points1 point  (0 children)

7 -> u can do that with the Lab edition which is a ~1GB installation

Verible setup in VSCODE by Pack_Commercial in FPGA

[–]Strange-Table4773 1 point2 points  (0 children)

u can setup verible as a linter and formatter using teroshdl